| /arch/sparc/kernel/ |
| D | head_64.S | 175 mov 1, %l3
176 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
177 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
199 mov 4, %l3
200 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
201 mov 1, %l3
202 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
206 mov 64, %l3
207 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, size
214 mov (1b - prom_boot_mapped_pc), %l3
[all …]
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| D | hvtramp.S | 58 add %l0, HVTRAMP_DESCR_MAPS, %l3
60 1: ldx [%l3 + HVTRAMP_MAPPING_VADDR], %o0
62 ldx [%l3 + HVTRAMP_MAPPING_TTE], %o2
73 add %l3, HVTRAMP_MAPPING_SIZE, %l3
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| D | trampoline_64.S | 129 sethi %hi(KERNBASE), %l3
161 add %l3, %g1, %g2
194 add %l3, %g1, %g2
221 sethi %hi(KERNBASE), %l3
231 add %l3, %g2, %o0
239 add %l3, %g2, %o0
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| D | urtt_fill.S | 38 mov %g3, %l3
64 brnz,pn %l3, 1f
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| D | entry.S | 82 sethi %hi(fdc_status), %l3
83 ld [%l3 + %lo(fdc_status)], %l3
91 ldub [%l3], %l7
102 ldub [%l3 + 1], %l7
115 stb %l7, [%l3 + 1]
176 rd %wim, %l3
1000 rd %wim, %l3
1205 rd %wim,%l3
1218 rd %wim,%l3
1290 rd %wim, %l3
[all …]
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| D | winfixup.S | 59 stx %l3, [%g3 + TI_REG_WINDOW + 0x18]
76 stw %l3, [%g3 + TI_REG_WINDOW + 0x0c]
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| D | rtrap_64.S | 139 andcc %l1, TSTATE_PRIV, %l3
191 brz,pt %l3, 1f
232 brnz,pn %l3, kern_rtt
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| D | etrap_64.S | 199 srl %l5, 1, %l3
205 stb %g0, [%l4 + %l3]
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| /arch/sparc/include/asm/ |
| D | head_32.h | 13 rd %psr, %l0; b label; rd %wim, %l3; nop;
16 #define SRMMU_TFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 1, %l7;
17 #define SRMMU_DFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 0, %l7;
21 rd %psr, %l0; mov num, %l7; b bad_trap_handler; rd %wim, %l3;
73 mov int_level, %l7; rd %psr, %l0; b real_irq_entry; rd %wim, %l3;
79 rd %psr, %l0; rd %wim, %l3; b spill_window_entry; andcc %l0, PSR_PS, %g0;
82 rd %psr, %l0; rd %wim, %l3; b fill_window_entry; andcc %l0, PSR_PS, %g0;
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| D | ttable.h | 20 clr %l0; clr %l1; clr %l2; clr %l3; \
255 stx %l3, [%sp + STACK_BIAS + 0x18]; \
276 stx %l3, [%sp + STACK_BIAS + 0x18]; \
304 stxa %l3, [%g1 + %g3] ASI; \
334 stxa %l3, [%sp + STACK_BIAS + 0x18] %asi; \
368 stx %l3, [%g3 + TI_REG_WINDOW + 0x18]; \
400 stwa %l3, [%g1 + %g3] ASI; \
433 stwa %l3, [%sp + 0x0c] %asi; \
467 stw %l3, [%g3 + TI_REG_WINDOW + 0x0c]; \
511 ldx [%sp + STACK_BIAS + 0x18], %l3; \
[all …]
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| /arch/sparc/power/ |
| D | hibernate_asm.S | 82 mov %g3, %l3 /* PAGE_SIZE-8 */
84 ldxa [%l1 + %l3] ASI_PHYS_USE_EC, %g2
85 stxa %g2, [%l2 + %l3] ASI_PHYS_USE_EC
86 cmp %l3, %g0
88 sub %l3, 8, %l3
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| /arch/x86/kernel/cpu/ |
| D | cacheinfo.c | 238 union l3_cache l3; in amd_cpuid4() local
246 cpuid(0x80000006, &dummy, &dummy, &l2.val, &l3.val); in amd_cpuid4()
270 if (!l3.val) in amd_cpuid4()
272 assoc = assocs[l3.assoc]; in amd_cpuid4()
273 line_size = l3.line_size; in amd_cpuid4()
274 lines_per_tag = l3.lines_per_tag; in amd_cpuid4()
275 size_in_kb = l3.size_encoded * 512; in amd_cpuid4()
308 struct amd_l3_cache *l3 = &nb->l3_cache; in amd_calc_l3_indices() local
315 l3->subcaches[0] = sc0 = !(val & BIT(0)); in amd_calc_l3_indices()
316 l3->subcaches[1] = sc1 = !(val & BIT(4)); in amd_calc_l3_indices()
[all …]
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| /arch/sparc/prom/ |
| D | cif.S | 21 mov %g6, %l3
26 mov %l3, %g6
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| /arch/sparc/lib/ |
| D | xor.S | 390 xor %l3, %l1, %l3
392 stxa %l3, [%i0 + 0x38] %asi
579 xor %l3, %l1, %l3
581 stxa %l3, [%i0 + 0x08] %asi
595 xor %l3, %l1, %l3
597 stxa %l3, [%i0 + 0x18] %asi
611 xor %l3, %l1, %l3
613 stxa %l3, [%i0 + 0x28] %asi
630 xor %l3, %l1, %l3
632 stxa %l3, [%i0 + 0x38] %asi
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| D | muldi3.S | 53 mov %o1, %l3
65 restore %g0, %l3, %o1
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| D | NGpage.S | 38 stxa %l3, [%i0 + 0x28] %asi
50 stxa %l3, [%i0 + 0x68] %asi
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| /arch/powerpc/kernel/ |
| D | setup_64.c | 571 struct device_node *cpu = NULL, *l2, *l3 = NULL; in initialize_cache_info() local
589 init_cache_info(&ppc64_caches.l3, 0x800000, 128, 0, 8192); in initialize_cache_info()
612 l3 = of_find_next_cache_node(l2); in initialize_cache_info()
615 if (l3) { in initialize_cache_info()
616 parse_cache_info(l3, false, &ppc64_caches.l3); in initialize_cache_info()
617 of_node_put(l3); in initialize_cache_info()
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| /arch/powerpc/include/asm/ |
| D | elf.h | 148 NEW_AUX_ENT(AT_L3_CACHESIZE, ppc64_caches.l3.size); \
149 NEW_AUX_ENT(AT_L3_CACHEGEOMETRY, get_cache_geometry(l3))
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| D | cache.h | 53 struct ppc_cache_info l3; member
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| /arch/arm/boot/dts/ |
| D | dra62x-clocks.dtsi | 5 /* Compared to dm814x, dra62x does not have hdic, l3 or dss PLLs */
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| D | gemini-wbd111.dts | 44 led-red-l3 {
62 led-greeb-l3 {
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| D | gemini-wbd222.dts | 43 led-red-l3 {
61 led-green-l3 {
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| D | am33xx-clocks.dtsi | 558 l3_clkctrl: l3-clkctrl@24 {
608 l3_aon_clkctrl: l3-aon-clkctrl@14 {
649 gfx_l3_cm: gfx-l3-cm@900 {
656 gfx_l3_clkctrl: gfx-l3-clkctrl@0 {
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| /arch/powerpc/boot/dts/fsl/ |
| D | b4420si-post.dtsi | 75 cpc: l3-cache-controller@10000 {
76 compatible = "fsl,b4420-l3-cache-controller", "cache";
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| /arch/arm64/boot/dts/ti/ |
| D | k3-am654.dtsi | 111 msmc_l3: l3-cache0 {
|