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/arch/powerpc/mm/ptdump/
Dbats.c24 static void bat_show_601(struct seq_file *m, int idx, u32 lower, u32 upper) in bat_show_601() argument
29 phys_addr_t pbn = PHYS_BAT_ADDR(lower); in bat_show_601()
30 u32 bsm = lower & 0x3ff; in bat_show_601()
34 if (!(lower & 0x40)) { in bat_show_601()
48 if (lower & _PAGE_WRITETHRU) in bat_show_601()
50 if (lower & _PAGE_NO_CACHE) in bat_show_601()
52 if (lower & _PAGE_COHERENT) in bat_show_601()
71 static void bat_show_603(struct seq_file *m, int idx, u32 lower, u32 upper, bool is_d) in bat_show_603() argument
76 phys_addr_t brpn = PHYS_BAT_ADDR(lower); in bat_show_603()
99 if (lower & BPP_RX) in bat_show_603()
[all …]
/arch/mips/include/asm/
Dmaar.h40 static inline void write_maar_pair(unsigned idx, phys_addr_t lower, in write_maar_pair() argument
44 BUG_ON(lower & (0xffff | ~(MIPS_MAAR_ADDR << 4))); in write_maar_pair()
60 write_c0_maar((lower >> 4) | attrs); in write_maar_pair()
87 phys_addr_t lower; member
109 write_maar_pair(i, cfg[i].lower, cfg[i].upper, cfg[i].attrs); in maar_config()
/arch/arm/kernel/
Dmodule.c82 u32 upper, lower, sign, j1, j2; in apply_relocate() local
219 lower = __mem_to_opcode_thumb16(*(u16 *)(loc + 2)); in apply_relocate()
235 j1 = (lower >> 13) & 1; in apply_relocate()
236 j2 = (lower >> 11) & 1; in apply_relocate()
240 ((lower & 0x07ff) << 1); in apply_relocate()
270 lower = (u16)((lower & 0xd000) | in apply_relocate()
275 *(u16 *)(loc + 2) = __opcode_to_mem_thumb16(lower); in apply_relocate()
281 lower = __mem_to_opcode_thumb16(*(u16 *)(loc + 2)); in apply_relocate()
295 ((lower & 0x7000) >> 4) | (lower & 0x00ff); in apply_relocate()
305 lower = (u16)((lower & 0x8f00) | in apply_relocate()
[all …]
Dmodule-plts.c126 u16 upper, lower; in is_zero_addend_relocation() local
131 lower = __mem_to_opcode_thumb16(((u16 *)tval)[1]); in is_zero_addend_relocation()
133 return (upper & 0x7ff) == 0x7ff && (lower & 0x2fff) == 0x2ffe; in is_zero_addend_relocation()
/arch/microblaze/kernel/
Dftrace.c175 unsigned int lower = (unsigned int)func; in ftrace_update_ftrace_func() local
180 lower = 0x32800000 + (lower & 0xFFFF); /* addik r20, r0, func_lower */ in ftrace_update_ftrace_func()
183 __func__, (unsigned int)func, (unsigned int)ip, upper, lower); in ftrace_update_ftrace_func()
187 ret += ftrace_modify_code(ip + 4, lower); in ftrace_update_ftrace_func()
/arch/mips/mm/
Dinit.c288 cfg->lower = ALIGN(PFN_PHYS(start_pfn), maar_align); in maar_res_walk()
319 phys_addr_t lower, upper, attr; in maar_init() local
364 lower = read_c0_maar(); in maar_init()
366 attr = lower & upper; in maar_init()
367 lower = (lower & MIPS_MAAR_ADDR) << 4; in maar_init()
376 pr_cont("%pa-%pa", &lower, &upper); in maar_init()
385 recorded.cfgs[recorded.used].lower = lower; in maar_init()
/arch/powerpc/include/asm/
Dtime.h129 static inline void set_tb(unsigned int upper, unsigned int lower) in set_tb() argument
133 mtspr(SPRN_TBWL, lower); in set_tb()
/arch/m68k/fpsp040/
Dbinstr.S52 | d3: lower 32-bits of fraction for mul by 8
54 | d5: lower 32-bits of fraction for mul by 2
99 swap %d6 |put 0 in d6 lower word
104 addl %d5,%d3 |add lower 32 bits
Dx_store.S160 lsll %d0,%d1 |put lower 11 bits in upper bits
161 movel %d1,LOCAL_HI(%a1) |build lower lword in memory
Dx_unfl.S190 | information respectively on upper/lower register halves.
193 | ;mode in lower d1
Dscale.S167 cmpiw #0xffc0,%d1 |lower bound for normalization
168 blt fix_unfl |if lower, catastrophic unfl
Dx_fline.S90 movew %d0,CMDREG1B(%a6) |move the lower word into CMDREG1B
Dres_func.S885 lsrl #4,%d0 |put rmode in lower 2 bits
909 lsrl #4,%d0 |put rmode in lower 2 bits
935 lsrl #4,%d0 |put rmode in lower 2 bits
1060 lsrl #4,%d0 |put rmode in lower 2 bits
1084 lsrl #4,%d0 |put rmode in lower 2 bits
1116 lsrl #4,%d0 |put rmode in lower 2 bits
1997 clrw 2(%a0) |clear lower word of exp
2004 clrw 2(%a0) |clear lower word of exp
2008 clrw 2(%a0) |clear lower word of exp
Dround.S53 bne rnd_cont |lower bits to zero for size
154 tstl LOCAL_LO(%a0) |test lower mantissa
163 movel LOCAL_LO(%a0),%d2 |get lower mantissa for s-bit test
385 lower: label
Dsint.S150 | rounding modes. L_SCR1 contains the rmode in the lower byte.
Dbindec.S115 | d3: scratch;lower 32-bits of mantissa for binstr
271 | loop entry A6. The lower word of d5 is used for ICTR.
638 swap %d5 |put ICTR in lower word of d5
/arch/x86/include/asm/
Dmpx.h62 void __user *lower; member
/arch/arm/lib/
Ddiv64.S93 @ See if we need to handle lower 32-bit result.
100 @ The division loop for lower bit positions.
116 @ Otherwise, if lower part is also null then we are done.
/arch/arm/include/debug/
Domap2plus.S66 strb \rd, [\rx] @ send lower byte of rd
/arch/xtensa/kernel/
Dalign.S203 and a3, a3, a7 # mask lower bits
260 extui a3, a3, 0, 16 # extract lower 16 bits
387 l32i a5, a4, 0 # load lower address word
/arch/powerpc/platforms/
DKconfig240 The TAU hardware can compare the temperature to an upper and lower
241 bound. The default behavior is to show both the upper and lower
246 halfway between the upper and lower bounds, will be reported in
/arch/mips/include/asm/mach-cavium-octeon/
Dkernel-entry-init.h31 # Clear the lower 6 bits, the CVMSEG size
/arch/arm/mach-omap2/
DKconfig230 SDRAM performance at lower CORE OPPs. There are relatively few
/arch/riscv/net/
Dbpf_jit_comp.c526 s64 upper = (val + (1 << 11)) >> 12, lower = val & 0xfff; in emit_imm() local
534 emit(rv_addi(rd, RV_REG_ZERO, lower), ctx); in emit_imm()
538 emit(rv_addiw(rd, rd, lower), ctx); in emit_imm()
549 if (lower) in emit_imm()
550 emit(rv_addi(rd, rd, lower), ctx); in emit_imm()
/arch/arm/boot/dts/
Dvf610-zii-dev-rev-c.dts218 /* lower */

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