| /arch/mips/alchemy/common/ |
| D | sleeper.S | 56 lw t0, 0(t1)
135 2: lw t1, 0x0850(a0) /* mem_sdstat */
143 lw t1, 0x0840(a0) /* mem_sdconfiga */
194 lw t0, 0x0848(a0) /* mem_sdconfigb */
208 3: lw t1, 0x0850(a0) /* mem_sdstat */
215 lw t1, 0x0840(a0) /* mem_sdconfiga */
230 lw k0, 0x20(sp)
232 lw k0, 0x1c(sp)
234 lw k0, 0x18(sp)
236 lw k0, 0x14(sp)
[all …]
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| /arch/mips/kernel/ |
| D | scall32-o32.S | 33 lw t1, PT_EPC(sp) # skip syscall on return
45 lw t0, PT_R29(sp) # get old user stack pointer
51 lw t5, TI_ADDR_LIMIT($28)
83 lw t0, TI_FLAGS($28) # syscall tracing enabled?
95 lw t2, (t1) # syscall routine
106 lw t1, PT_R2(sp) # syscall number
127 lw a1, PT_R4(sp)
134 lw v0, PT_R2(sp) # Restore syscall (maybe modified)
135 lw a0, PT_R4(sp) # Restore argument registers
136 lw a1, PT_R5(sp)
[all …]
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| D | cpu-bugs64.c | 48 long p, s, lv1, lv2, lw; in mult_sh_align_mod() local
91 : "=&r" (lv1), "=r" (lw) in mult_sh_align_mod()
115 *w = lw; in mult_sh_align_mod()
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| D | cps-vec.S | 126 lw s7, GCR_CL_COHERENCE_OFS(v1)
310 lw t0, GCR_CL_ID_OFS(t0)
362 lw ta2, COREBOOTCFG_VPEMASK(a0)
437 lw t1, VPEBOOTCFG_PC(t0)
441 lw t1, VPEBOOTCFG_SP(t0)
445 lw t1, VPEBOOTCFG_GP(t0)
604 lw $1, TI_CPU(gp)
608 lw $1, 0($1)
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| D | scall64-o32.S | 69 load_a4: lw a4, 16(t0) # argument #5 from usp
70 load_a5: lw a5, 20(t0) # argument #6 from usp
71 load_a6: lw a6, 24(t0) # argument #7 from usp
72 load_a7: lw a7, 28(t0) # argument #8 from usp
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| D | bmips_vec.S | 212 lw k0, 0(k0)
234 lw sp, 0(k0)
236 lw gp, 0(k0)
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| D | r2300_switch.S | 58 lw a2, THREAD_STATUS(a1)
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| D | r4k_fpu.S | 171 EX lw t1, 0(a1)
359 EX lw $1, \off(\base)
361 EX lw $1, (\off+4)(\base)
364 EX lw $1, (\off+4)(\base)
366 EX lw $1, \off(\base)
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| D | genex.S | 86 lw k1, (k0)
97 lw k1, (k0)
614 lw k1, (k1)
620 lw k1, (k1)
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| D | head.S | 107 lw t0, (t2)
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| /arch/mips/dec/ |
| D | int-handler.S | 135 lw t2,cpu_fpu_mask
214 2: lw t2,(t1)
223 lw a0,%lo(-PTRSIZE)(t1)
285 lw t0,fpu_kstat_irq
287 lw t1,(t0)
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| /arch/mips/kvm/ |
| D | msa.S | 100 lw $1, \off(\base)
102 lw $1, (\off+4)(\base)
105 lw $1, (\off+4)(\base)
107 lw $1, \off(\base)
151 lw t0, VCPU_MSA_CSR(a0)
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| /arch/mips/include/asm/ |
| D | asm.h | 155 #define REG_L lw
176 #define INT_L lw
213 #define LONG_L lw
262 #define PTR_L lw
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| D | ftrace.h | 67 safe_load(STR(lw), src, dst, error)
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| /arch/mips/netlogic/common/ |
| D | reset.S | 197 lw t1, 0(t2)
202 lw t1, 0(t2)
221 lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */
247 lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */
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| D | smpboot.S | 128 lw v1, BOOT_THREAD_MODE(v0) /* v1 - new thread mode */
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| /arch/mips/include/asm/mach-malta/ |
| D | kernel-entry-init.h | 114 lw v0, (v0)
120 lw v0, (v0)
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| /arch/alpha/include/asm/ |
| D | agp_backend.h | 17 u32 lw; member
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| /arch/microblaze/lib/ |
| D | fastcopy.S | 272 lw r9, r6, r10 /* t1 = *(s+offset) */
293 lw r12, r8, r10 /* v = *(as + offset) */
307 lw r12, r8, r10 /* v = *(as + offset) */
321 lw r12, r8, r10 /* v = *(as + offset) */
597 lw r9, r6, r4 /* t1 = *(s+n) */
605 lw r11, r8, r4 /* h = *(as + n) */
616 lw r12, r8, r4 /* v = *(as + n) */
629 lw r12, r8, r4 /* v = *(as + n) */
642 lw r12, r8, r4 /* v = *(as + n) */
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| /arch/riscv/include/asm/ |
| D | asm.h | 23 #define REG_L __REG_SEL(ld, lw)
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| /arch/nds32/kernel/ |
| D | ex-entry.S | 81 lw $r25, [$p0]
114 lw $p1, [$p1+$p0<<2]
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| /arch/microblaze/kernel/ |
| D | head.S | 92 lw r11, r0, r7 /* Big endian load in delay slot */
104 lw r12, r7, r11 /* r12 = r7 + r11 */
142 lw r7, r0, r11 /* r7 = r0 + r6 */
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| /arch/mips/net/ |
| D | bpf_jit_asm.S | 66 lw $r_A, 0(t1)
264 lw $r_A, 0($r_s0)
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| /arch/mips/lib/ |
| D | csum_partial.S | 50 #define LOAD lw
51 #define LOAD32 lw
163 lw t0, 0x00(src)
164 lw t1, 0x04(src)
405 #define LOADK lw /* No exception */
406 #define LOAD(reg, addr, handler) EXC(lw, LD_INSN, reg, addr, handler)
461 lw errptr, 16(sp)
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| /arch/mips/fw/lib/ |
| D | call_o32.S | 77 lw t3,(t0)
|