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Searched refs:mtctl (Results 1 – 18 of 18) sorted by relevance

/arch/parisc/kernel/
Dhead.S75 mtctl %r10,%cr11
114 mtctl %r4,%cr24 /* Initialize kernel root pointer */
115 mtctl %r4,%cr25 /* Initialize user root pointer */
167 mtctl %r6,%cr30
259 mtctl %r6,%cr30 /* restore task thread info */
275 mtctl %r0,%cr8
276 mtctl %r0,%cr9
277 mtctl %r0,%cr12
278 mtctl %r0,%cr13
291 mtctl %r10,%cr11
[all …]
Dreal2.S120 # define POP_CR(r, where) LDREG,mb -REG_SZ(where), %r1 ! mtctl %r1, r
170 mtctl %r0, %cr17 /* Clear IIASQ tail */
171 mtctl %r0, %cr17 /* Clear IIASQ head */
172 mtctl %r1, %cr18 /* IIAOQ head */
174 mtctl %r1, %cr18 /* IIAOQ tail */
176 mtctl %r1, %cr22
207 mtctl %r0, %cr17 /* Clear IIASQ tail */
208 mtctl %r0, %cr17 /* Clear IIASQ head */
209 mtctl %r1, %cr18 /* IIAOQ head */
211 mtctl %r1, %cr18 /* IIAOQ tail */
[all …]
Drelocate_kernel.S62 mtctl %r0, %cr17 /* IIASQ */
63 mtctl %r0, %cr17 /* IIASQ */
64 mtctl %r1, %cr18 /* IIAOQ */
66 mtctl %r1, %cr18 /* IIAOQ */
69 mtctl %r1, %cr22 /* IPSW */
71 mtctl %r0, %cr22 /* IPSW */
133 mtctl %r0, %cr15
Dhpmc.S128 mtctl %r4,ipsw
129 mtctl %r0,pcsq
130 mtctl %r0,pcsq
132 mtctl %r4,pcoq
134 mtctl %r4,pcoq
237 mtctl %r4,%cr24 /* Initialize kernel root pointer */
238 mtctl %r4,%cr25 /* Initialize user root pointer */
Dtime.c118 mtctl(next_tick, 16); in timer_interrupt()
161 mtctl(next_tick, 16); /* kick off Interval Timer (CR16) */ in start_cpu_itimer()
Dpacache.S52 mtctl %r0, %cr17 /* Clear IIASQ tail */
53 mtctl %r0, %cr17 /* Clear IIASQ head */
54 mtctl %r1, %cr18 /* IIAOQ head */
56 mtctl %r1, %cr18 /* IIAOQ tail */
58 mtctl %r1, %ipsw
164 mtctl %r0, %cr17 /* Clear IIASQ tail */
165 mtctl %r0, %cr17 /* Clear IIASQ head */
166 mtctl %r1, %cr18 /* IIAOQ head */
168 mtctl %r1, %cr18 /* IIAOQ tail */
171 mtctl %r1, %ipsw /* restore I-bit (entire PSW) */
[all …]
Dkgdb.c200 mtctl(-1, 0); in kgdb_arch_handle_exception()
202 mtctl(0, 0); in kgdb_arch_handle_exception()
Dperf_asm.S43 mtctl %r26,ccr ; turn on performance coprocessor
48 mtctl %r26,ccr ; turn off performance coprocessor
69 mtctl %r26,ccr ; turn on performance coprocessor
74 mtctl %r26,ccr ; turn off performance coprocessor
Dentry.S67 mtctl %r0, %cr17 /* Clear IIASQ tail */
68 mtctl %r0, %cr17 /* Clear IIASQ head */
69 mtctl %r1, %ipsw
71 mtctl %r1, %cr18 /* Set IIAOQ tail */
73 mtctl %r1, %cr18 /* Set IIAOQ head */
806 mtctl %r25,%cr30
809 mtctl %r0, %cr0 /* Needed for single stepping */
1372 mtctl %r8,%ipsw
1749 mtctl %r3, %cr27
1903 mtctl %r2,%cr0 /* for immediate trap */
[all …]
Dirq.c82 mtctl(mask, 23); in cpu_ack_irq()
600 mtctl(~0UL, 23); /* EIRR : clear all pending external intr */ in init_IRQ()
Dsetup.c403 mtctl(coproc_cfg.ccr_functional, 10); in start_parisc()
Dkprobes.c77 mtctl(0, 0); in setup_singlestep()
Dprocessor.c331 mtctl(coproc_cfg.ccr_functional, 10); /* 10 == Coprocessor Control Reg */ in init_per_cpu()
Dsignal.c384 mtctl(-1, 0); in setup_rt_frame()
Dsyscall.S94 mtctl %r26, %cr27 /* move arg0 to the control register */
/arch/parisc/include/asm/
Dspecial_insns.h38 #define mtctl(gr, cr) \ macro
48 mtctl(val, 15); in set_eiem()
Dmmu_context.h50 mtctl(__space_to_prot(context), 8); in load_context()
57 mtctl(__pa(next->pgd), 25); in switch_mm_irqs_off()
Dassembly.h160 #define REST_CR(r, where) LDREG where, %r1 ! mtctl %r1, r
365 mtctl %r3, %cr27
409 mtctl %r3, %cr27
425 mtctl %r0, %cr17
429 mtctl %r0, %cr18