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/arch/alpha/lib/
Dmemcpy.c26 #define ALIGN_DEST_TO8_UP(d,s,n) \ argument
28 if (n <= 0) return; \
29 n--; \
33 #define ALIGN_DEST_TO8_DN(d,s,n) \ argument
35 if (n <= 0) return; \
36 n--; \
45 #define DO_REST_UP(d,s,n) \ argument
46 while (n > 0) { \
47 n--; \
51 #define DO_REST_DN(d,s,n) \ argument
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/arch/mips/loongson32/common/
Dirq.c13 #define LS1X_INTC_REG(n, x) \ argument
14 ((void __iomem *)KSEG1ADDR(LS1X_INTC_BASE + (n * 0x18) + (x)))
16 #define LS1X_INTC_INTISR(n) LS1X_INTC_REG(n, 0x0) argument
17 #define LS1X_INTC_INTIEN(n) LS1X_INTC_REG(n, 0x4) argument
18 #define LS1X_INTC_INTSET(n) LS1X_INTC_REG(n, 0x8) argument
19 #define LS1X_INTC_INTCLR(n) LS1X_INTC_REG(n, 0xc) argument
20 #define LS1X_INTC_INTPOL(n) LS1X_INTC_REG(n, 0x10) argument
21 #define LS1X_INTC_INTEDGE(n) LS1X_INTC_REG(n, 0x14) argument
26 unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5; in ls1x_irq_ack() local
28 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) in ls1x_irq_ack()
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/arch/arm/include/debug/
Dimx-uart.h11 #define IMX1_UART_BASE_ADDR(n) IMX1_UART##n##_BASE_ADDR argument
12 #define IMX1_UART_BASE(n) IMX1_UART_BASE_ADDR(n) argument
18 #define IMX21_UART_BASE_ADDR(n) IMX21_UART##n##_BASE_ADDR argument
19 #define IMX21_UART_BASE(n) IMX21_UART_BASE_ADDR(n) argument
26 #define IMX25_UART_BASE_ADDR(n) IMX25_UART##n##_BASE_ADDR argument
27 #define IMX25_UART_BASE(n) IMX25_UART_BASE_ADDR(n) argument
34 #define IMX31_UART_BASE_ADDR(n) IMX31_UART##n##_BASE_ADDR argument
35 #define IMX31_UART_BASE(n) IMX31_UART_BASE_ADDR(n) argument
40 #define IMX35_UART_BASE_ADDR(n) IMX35_UART##n##_BASE_ADDR argument
41 #define IMX35_UART_BASE(n) IMX35_UART_BASE_ADDR(n) argument
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/arch/powerpc/include/asm/
Dppc_asm.h77 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
78 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
82 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
83 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
88 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
89 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
90 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
91 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
92 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
93 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
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/arch/arm/mach-mmp/
Dregs-timers.h15 #define TMR_TN_MM(n, m) (0x0004 + ((n) << 3) + (((n) + (m)) << 2)) argument
16 #define TMR_CR(n) (0x0028 + ((n) << 2)) argument
17 #define TMR_SR(n) (0x0034 + ((n) << 2)) argument
18 #define TMR_IER(n) (0x0040 + ((n) << 2)) argument
19 #define TMR_PLVR(n) (0x004c + ((n) << 2)) argument
20 #define TMR_PLCR(n) (0x0058 + ((n) << 2)) argument
25 #define TMR_ICR(n) (0x0074 + ((n) << 2)) argument
29 #define TMR_ILR(n) (0x008c + ((n) << 2)) argument
33 #define TMR_CVWR(n) (0x00A4 + ((n) << 2)) argument
/arch/powerpc/perf/
Dbhrb.S32 #define MFBHRB_TABLE1(n) PPC_MFBHRBE(R3,n); blr argument
33 #define MFBHRB_TABLE2(n) MFBHRB_TABLE1(n); MFBHRB_TABLE1(n+1) argument
34 #define MFBHRB_TABLE4(n) MFBHRB_TABLE2(n); MFBHRB_TABLE2(n+2) argument
35 #define MFBHRB_TABLE8(n) MFBHRB_TABLE4(n); MFBHRB_TABLE4(n+4) argument
36 #define MFBHRB_TABLE16(n) MFBHRB_TABLE8(n); MFBHRB_TABLE8(n+8) argument
37 #define MFBHRB_TABLE32(n) MFBHRB_TABLE16(n); MFBHRB_TABLE16(n+16) argument
/arch/x86/boot/compressed/
Dstring.c14 static void *____memcpy(void *dest, const void *src, size_t n) in ____memcpy() argument
22 : "0" (n >> 2), "g" (n & 3), "1" (dest), "2" (src) in ____memcpy()
28 static void *____memcpy(void *dest, const void *src, size_t n) in ____memcpy() argument
36 : "0" (n >> 3), "g" (n & 7), "1" (dest), "2" (src) in ____memcpy()
43 void *memset(void *s, int c, size_t n) in memset() argument
48 for (i = 0; i < n; i++) in memset()
53 void *memmove(void *dest, const void *src, size_t n) in memmove() argument
58 if (d <= s || d - s >= n) in memmove()
59 return ____memcpy(dest, src, n); in memmove()
61 while (n-- > 0) in memmove()
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/arch/m68k/include/asm/
Dide.h50 #define __ide_mm_insw(port, addr, n) raw_insw((u16 *)port, addr, n) argument
51 #define __ide_mm_insl(port, addr, n) raw_insl((u32 *)port, addr, n) argument
54 #define __ide_mm_outsw(port, addr, n) raw_outsw((u16 *)port, addr, n) argument
55 #define __ide_mm_outsl(port, addr, n) raw_outsl((u32 *)port, addr, n) argument
59 #define __ide_mm_insw(port, addr, n) io_insw((unsigned int)port, addr, n) argument
60 #define __ide_mm_insl(port, addr, n) io_insl((unsigned int)port, addr, n) argument
61 #define __ide_mm_outsw(port, addr, n) io_outsw((unsigned int)port, addr, n) argument
62 #define __ide_mm_outsl(port, addr, n) io_outsl((unsigned int)port, addr, n) argument
/arch/x86/lib/
Diomem.c9 static __always_inline void rep_movs(void *to, const void *from, size_t n) in rep_movs() argument
21 : "0" (n / 4), "q" (n), "1" ((long)to), "2" ((long)from) in rep_movs()
25 void memcpy_fromio(void *to, const volatile void __iomem *from, size_t n) in memcpy_fromio() argument
27 if (unlikely(!n)) in memcpy_fromio()
33 n--; in memcpy_fromio()
35 if (n > 1 && unlikely(2 & (unsigned long)from)) { in memcpy_fromio()
37 n-=2; in memcpy_fromio()
39 rep_movs(to, (const void *)from, n); in memcpy_fromio()
43 void memcpy_toio(volatile void __iomem *to, const void *from, size_t n) in memcpy_toio() argument
45 if (unlikely(!n)) in memcpy_toio()
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/arch/um/kernel/skas/
Duaccess.c64 int n; in do_op_one_page() local
79 n = (*op)(addr, len, arg); in do_op_one_page()
87 return n; in do_op_one_page()
93 long size, remain, n; in buffer_op() local
98 n = do_op_one_page(addr, size, is_write, op, arg); in buffer_op()
99 if (n != 0) { in buffer_op()
100 remain = (n < 0 ? remain : 0); in buffer_op()
110 n = do_op_one_page(addr, PAGE_SIZE, is_write, op, arg); in buffer_op()
111 if (n != 0) { in buffer_op()
112 remain = (n < 0 ? remain : 0); in buffer_op()
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/arch/csky/lib/
Dusercopy.c8 unsigned long n) in raw_copy_from_user() argument
10 ___copy_from_user(to, from, n); in raw_copy_from_user()
11 return n; in raw_copy_from_user()
16 unsigned long n) in raw_copy_to_user() argument
18 ___copy_to_user(to, from, n); in raw_copy_to_user()
19 return n; in raw_copy_to_user()
129 long strnlen_user(const char *s, long n) in strnlen_user() argument
157 : "=r"(n), "=r"(s), "=r"(res), "=r"(tmp) in strnlen_user()
158 : "0"(n), "1"(s), "2"(n) in strnlen_user()
233 clear_user(void __user *to, unsigned long n) in clear_user() argument
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/arch/ia64/kernel/
Dmca_drv.h57 #define peidx_cache_check_idx(p, n) (n) argument
58 #define peidx_tlb_check_idx(p, n) (peidx_cache_check_idx(p, peidx_cache_check_num(p)) + n) argument
59 #define peidx_bus_check_idx(p, n) (peidx_tlb_check_idx(p, peidx_tlb_check_num(p)) + n) argument
60 #define peidx_reg_file_check_idx(p, n) (peidx_bus_check_idx(p, peidx_bus_check_num(p)) + n) argument
61 #define peidx_ms_check_idx(p, n) (peidx_reg_file_check_idx(p, peidx_reg_file_check_num(p)) + … argument
63 #define peidx_mod_error_info(p, name, n) \ argument
64 ({ int __idx = peidx_##name##_idx(p, n); \
66 if (peidx_##name##_num(p) > n) /*BUG*/ \
70 #define peidx_cache_check(p, n) peidx_mod_error_info(p, cache_check, n) argument
71 #define peidx_tlb_check(p, n) peidx_mod_error_info(p, tlb_check, n) argument
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/arch/arc/include/asm/
Duaccess.h168 raw_copy_from_user(void *to, const void __user *from, unsigned long n) in raw_copy_from_user() argument
173 unsigned long orig_n = n; in raw_copy_from_user()
175 if (n == 0) in raw_copy_from_user()
199 : "+r" (n), in raw_copy_from_user()
209 return n; in raw_copy_from_user()
248 : "ir"(n) in raw_copy_from_user()
385 : "=r" (res), "+r"(to), "+r"(from), "+r"(n), "=r"(val), in raw_copy_from_user()
395 raw_copy_to_user(void __user *to, const void *from, unsigned long n) in raw_copy_to_user() argument
400 unsigned long orig_n = n; in raw_copy_to_user()
402 if (n == 0) in raw_copy_to_user()
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/arch/arm/include/asm/
Ddelay.h58 #define __delay(n) arm_delay_ops.delay(n) argument
79 #define __udelay(n) arm_delay_ops.udelay(n) argument
80 #define __const_udelay(n) arm_delay_ops.const_udelay(n) argument
82 #define udelay(n) \ argument
83 (__builtin_constant_p(n) ? \
84 ((n) > (MAX_UDELAY_MS * 1000) ? __bad_udelay() : \
85 __const_udelay((n) * UDELAY_MULT)) : \
86 __udelay(n))
Ddiv64.h33 static inline uint32_t __div64_32(uint64_t *n, uint32_t base) in __div64_32() argument
36 register unsigned long long __n asm("r0") = *n; in __div64_32()
47 *n = __res; in __div64_32()
60 #define do_div(n, base) __div64_32(&(n), base) argument
75 static inline uint64_t __arch_xprod_64(uint64_t m, uint64_t n, bool bias) in __arch_xprod_64() argument
84 : "r" (m), "r" (n) in __arch_xprod_64()
91 : "r" (m), "r" (n) in __arch_xprod_64()
99 : "r" (m), "r" (n) in __arch_xprod_64()
109 : "r" (m), "r" (n) in __arch_xprod_64()
119 : "r" (m), "r" (n) in __arch_xprod_64()
/arch/powerpc/kvm/
Dbook3s_32_sr.S30 #define XCHG_SR(n) lwz r9, (SVCPU_SR+(n*4))(r3); \ argument
31 mtsr n, r9
52 #define KVM_KILL_BAT(n, reg) \ argument
53 mtspr SPRN_IBAT##n##U,reg; \
54 mtspr SPRN_IBAT##n##L,reg; \
55 mtspr SPRN_DBAT##n##U,reg; \
56 mtspr SPRN_DBAT##n##L,reg; \
92 #define KVM_LOAD_BAT(n, reg, RA, RB) \ argument
93 lwz RA,(n*16)+0(reg); \
94 lwz RB,(n*16)+4(reg); \
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/arch/m68k/lib/
Dmemmove.c10 void *memmove(void *dest, const void *src, size_t n) in memmove() argument
15 if (!n) in memmove()
25 n--; in memmove()
27 if (n > 2 && (long)dest & 2) { in memmove()
33 n -= 2; in memmove()
35 temp = n >> 2; in memmove()
46 if (n & 2) { in memmove()
53 if (n & 1) { in memmove()
59 dest = (char *)dest + n; in memmove()
60 src = (const char *)src + n; in memmove()
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/arch/mips/ath79/
DKconfig6 def_bool n
11 def_bool n
14 def_bool n
17 def_bool n
22 def_bool n
27 def_bool n
30 def_bool n
33 def_bool n
36 def_bool n
39 def_bool n
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/arch/mips/include/asm/
Dkvm_para.h18 register unsigned long n asm("v0"); in kvm_hypercall0()
21 n = num; in kvm_hypercall0()
24 : "=r" (r) : "r" (n) : "memory" in kvm_hypercall0()
33 register unsigned long n asm("v0"); in kvm_hypercall1()
37 n = num; in kvm_hypercall1()
41 : "=r" (r) : "r" (n), "r" (a0) : "memory" in kvm_hypercall1()
50 register unsigned long n asm("v0"); in kvm_hypercall2()
55 n = num; in kvm_hypercall2()
60 : "=r" (r) : "r" (n), "r" (a0), "r" (a1) : "memory" in kvm_hypercall2()
69 register unsigned long n asm("v0"); in kvm_hypercall3()
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/arch/arm/lib/
Duaccess_with_memcpy.c85 __copy_to_user_memcpy(void __user *to, const void *from, unsigned long n) in __copy_to_user_memcpy() argument
91 memcpy((void *)to, from, n); in __copy_to_user_memcpy()
100 while (n) { in __copy_to_user_memcpy()
115 if (tocopy > n) in __copy_to_user_memcpy()
116 tocopy = n; in __copy_to_user_memcpy()
123 n -= tocopy; in __copy_to_user_memcpy()
134 return n; in __copy_to_user_memcpy()
138 arm_copy_to_user(void __user *to, const void *from, unsigned long n) in arm_copy_to_user() argument
147 if (n < 64) { in arm_copy_to_user()
149 n = __copy_to_user_std(to, from, n); in arm_copy_to_user()
[all …]
/arch/microblaze/include/asm/
Ddelay.h64 #define udelay(n) \ argument
66 if (__builtin_constant_p(n)) { \
67 if ((n) / __MAX_UDELAY >= 1) \
70 __udelay((n) * (19 * HZ)); \
72 __udelay((n) * (19 * HZ)); \
76 #define ndelay(n) \ argument
78 if (__builtin_constant_p(n)) { \
79 if ((n) / __MAX_NDELAY >= 1) \
82 __udelay((n) * HZ); \
84 __udelay((n) * HZ); \
/arch/arm/mach-lpc32xx/
Dlpc32xx.h14 #define _BIT(n) _SBF(n, 1) argument
284 #define LPC32XX_CLKPWR_HCLKDIV_PCLK_DIV(n) (((n) & 0x1F) << 2) argument
285 #define LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(n) ((n) & 0x3) argument
321 #define LPC32XX_CLKPWR_MOSC_ADD_CAP(n) (((n) & 0x7F) << 2) argument
329 #define LPC32XX_CLKPWR_SYSCTRL_BP_TRIG(n) (((n) & 0x3FF) << 2) argument
347 #define LPC32XX_CLKPWR_LCDCTRL_SET_PSCALE(n) ((n - 1) & 0x1F) argument
357 #define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(n) (((n) & 0x3) << 11) argument
358 #define LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(n) (((n) & 0x3) << 9) argument
359 #define LPC32XX_CLKPWR_HCLKPLL_PLLM(n) (((n) & 0xFF) << 1) argument
365 #define LPC32XX_CLKPWR_ADCCTRL1_RTDIV(n) (((n) & 0xFF) << 0) argument
[all …]
/arch/powerpc/kernel/
Dio.c123 _memset_io(volatile void __iomem *addr, int c, unsigned long n) in _memset_io() argument
131 while(n && !IO_CHECK_ALIGN(p, 4)) { in _memset_io()
134 n--; in _memset_io()
136 while(n >= 4) { in _memset_io()
139 n -= 4; in _memset_io()
141 while(n) { in _memset_io()
144 n--; in _memset_io()
151 unsigned long n) in _memcpy_fromio() argument
156 while(n && (!IO_CHECK_ALIGN(vsrc, 4) || !IO_CHECK_ALIGN(dest, 4))) { in _memcpy_fromio()
161 n--; in _memcpy_fromio()
[all …]
Deeh_cache.c56 struct rb_node *n = pci_io_addr_cache_root.rb_root.rb_node; in __eeh_addr_cache_get_device() local
58 while (n) { in __eeh_addr_cache_get_device()
60 piar = rb_entry(n, struct pci_io_addr_range, rb_node); in __eeh_addr_cache_get_device()
63 n = n->rb_left; in __eeh_addr_cache_get_device()
65 n = n->rb_right; in __eeh_addr_cache_get_device()
100 struct rb_node *n; in eeh_addr_cache_print() local
103 n = rb_first(&cache->rb_root); in eeh_addr_cache_print()
104 while (n) { in eeh_addr_cache_print()
106 piar = rb_entry(n, struct pci_io_addr_range, rb_node); in eeh_addr_cache_print()
111 n = rb_next(n); in eeh_addr_cache_print()
[all …]
/arch/x86/events/
Dperf_event.h280 #define __EVENT_CONSTRAINT_RANGE(c, e, n, m, w, o, f) { \ argument
281 { .idxmsk64 = (n) }, \
290 #define __EVENT_CONSTRAINT(c, n, m, w, o, f) \ argument
291 __EVENT_CONSTRAINT_RANGE(c, c, n, m, w, o, f)
293 #define EVENT_CONSTRAINT(c, n, m) \ argument
294 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0)
300 #define EVENT_CONSTRAINT_RANGE(c, e, n, m) \ argument
301 __EVENT_CONSTRAINT_RANGE(c, e, n, m, HWEIGHT(n), 0, 0)
303 #define INTEL_EXCLEVT_CONSTRAINT(c, n) \ argument
304 __EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\
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