Searched refs:parents (Results 1 – 25 of 171) sorted by relevance
1234567
/arch/arm/boot/dts/ |
D | imx7ulp.dtsi | 162 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; 174 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; 183 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; 234 assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>; 250 assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>; 288 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; 337 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; 349 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; 361 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; 373 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
|
D | exynos5422-odroidxu3-audio.dtsi | 41 assigned-clock-parents = <&clock CLK_FOUT_EPLL>, 88 assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>;
|
D | exynos5422-odroidxu4.dts | 47 assigned-clock-parents = <&clock CLK_FOUT_EPLL>, 82 assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>;
|
D | imx6qp-zii-rdu2.dts | 24 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD1_594M>;
|
D | imx7d-meerkat96.dts | 144 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 152 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 161 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 169 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
|
D | imx7d-pico.dtsi | 77 assigned-clock-parents = <&clks IMX7D_CKIL>; 93 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; 238 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; 270 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 278 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; 287 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
|
D | stih407.dtsi | 28 assigned-clock-parents = <0>, 95 assigned-clock-parents = <&clk_s_d2_quadfs 0>,
|
D | exynos4412-odroid-common.dtsi | 155 assigned-clock-parents = <&clock CLK_FOUT_EPLL>, 204 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; 212 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; 220 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; 228 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; 514 assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>;
|
D | exynos4412-itop-elite.dts | 131 assigned-clock-parents = <&clock CLK_XUSBXTI>; 139 assigned-clock-parents = <&clock CLK_FOUT_EPLL>, 161 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
|
D | imx6ull-colibri-wifi.dtsi | 42 assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
|
D | imx7d-nitrogen7.dts | 116 assigned-clock-parents = <&clks IMX7D_CKIL>; 129 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; 319 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; 327 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; 335 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; 343 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
|
D | imx7d-zii-rmu2.dts | 59 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; 196 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; 204 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
|
D | imx7d-cl-som-imx7.dts | 45 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; 73 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; 194 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
|
D | imx7-mba7.dtsi | 487 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; 495 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; 503 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; 511 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; 519 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
|
D | mt7629.dtsi | 101 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>; 255 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>; 309 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>, 371 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL2_D4>, 456 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
|
D | imx7d-zii-rpu2.dts | 213 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; 296 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; 570 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; 580 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; 590 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; 599 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; 607 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
|
D | imx7s-warp.dts | 270 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; 279 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 287 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 296 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
|
D | exynos4210-trats.dts | 210 assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 218 assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 226 assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 234 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
|
D | omap2420-n810.dts | 65 assigned-clock-parents = <&func_96m_ck>;
|
D | omap443x.dtsi | 87 assigned-clock-parents = <&dpll_per_m7x2_ck>;
|
/arch/arm64/boot/dts/amlogic/ |
D | meson-gxl-s805x.dtsi | 18 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
|
D | meson-gxl-mali.dtsi | 36 assigned-clock-parents = <0>, /* Do Nothing */
|
/arch/arm64/boot/dts/freescale/ |
D | imx8mq-hummingboard-pulse.dts | 99 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; 107 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
|
/arch/mips/boot/dts/ingenic/ |
D | gcw0.dts | 53 assigned-clock-parents =
|
/arch/arm64/boot/dts/exynos/ |
D | exynos5433-tm2e.dts | 37 assigned-clock-parents = <0>, <0>,
|
1234567