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Searched refs:parents (Results 1 – 25 of 171) sorted by relevance

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/arch/arm/boot/dts/
Dimx7ulp.dtsi162 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
174 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
183 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
234 assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
250 assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
288 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
337 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
349 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
361 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
373 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
Dexynos5422-odroidxu3-audio.dtsi41 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
88 assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>;
Dexynos5422-odroidxu4.dts47 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
82 assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>;
Dimx6qp-zii-rdu2.dts24 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD1_594M>;
Dimx7d-meerkat96.dts144 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
152 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
161 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
169 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
Dimx7d-pico.dtsi77 assigned-clock-parents = <&clks IMX7D_CKIL>;
93 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
238 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
270 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
278 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
287 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
Dstih407.dtsi28 assigned-clock-parents = <0>,
95 assigned-clock-parents = <&clk_s_d2_quadfs 0>,
Dexynos4412-odroid-common.dtsi155 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
204 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
212 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
220 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
228 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
514 assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>;
Dexynos4412-itop-elite.dts131 assigned-clock-parents = <&clock CLK_XUSBXTI>;
139 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
161 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
Dimx6ull-colibri-wifi.dtsi42 assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
Dimx7d-nitrogen7.dts116 assigned-clock-parents = <&clks IMX7D_CKIL>;
129 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
319 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
327 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
335 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
343 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
Dimx7d-zii-rmu2.dts59 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
196 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
204 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
Dimx7d-cl-som-imx7.dts45 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
73 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
194 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
Dimx7-mba7.dtsi487 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
495 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
503 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
511 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
519 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
Dmt7629.dtsi101 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
255 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
309 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
371 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL2_D4>,
456 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
Dimx7d-zii-rpu2.dts213 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
296 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
570 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
580 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
590 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
599 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
607 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
Dimx7s-warp.dts270 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
279 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
287 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
296 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
Dexynos4210-trats.dts210 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
218 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
226 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
234 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
Domap2420-n810.dts65 assigned-clock-parents = <&func_96m_ck>;
Domap443x.dtsi87 assigned-clock-parents = <&dpll_per_m7x2_ck>;
/arch/arm64/boot/dts/amlogic/
Dmeson-gxl-s805x.dtsi18 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
Dmeson-gxl-mali.dtsi36 assigned-clock-parents = <0>, /* Do Nothing */
/arch/arm64/boot/dts/freescale/
Dimx8mq-hummingboard-pulse.dts99 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
107 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
/arch/mips/boot/dts/ingenic/
Dgcw0.dts53 assigned-clock-parents =
/arch/arm64/boot/dts/exynos/
Dexynos5433-tm2e.dts37 assigned-clock-parents = <0>, <0>,

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