| /arch/mips/ath79/ |
| D | clock.c | 99 u32 pll; in ar71xx_clocks_init() local
105 pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG); in ar71xx_clocks_init()
107 div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1; in ar71xx_clocks_init()
110 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; in ar71xx_clocks_init()
113 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; in ar71xx_clocks_init()
116 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; in ar71xx_clocks_init()
127 u32 pll; in ar724x_clocks_init() local
131 pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG); in ar724x_clocks_init()
133 mult = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK); in ar724x_clocks_init()
134 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2; in ar724x_clocks_init()
[all …]
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| /arch/m68k/q40/ |
| D | config.c | 45 static int q40_get_rtc_pll(struct rtc_pll_info *pll);
46 static int q40_set_rtc_pll(struct rtc_pll_info *pll);
263 static int q40_get_rtc_pll(struct rtc_pll_info *pll) in q40_get_rtc_pll() argument
267 pll->pll_ctrl = 0; in q40_get_rtc_pll()
268 pll->pll_value = tmp & Q40_RTC_PLL_MASK; in q40_get_rtc_pll()
270 pll->pll_value = -pll->pll_value; in q40_get_rtc_pll()
271 pll->pll_max = 31; in q40_get_rtc_pll()
272 pll->pll_min = -31; in q40_get_rtc_pll()
273 pll->pll_posmult = 512; in q40_get_rtc_pll()
274 pll->pll_negmult = 256; in q40_get_rtc_pll()
[all …]
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| /arch/m68k/kernel/ |
| D | time.c | 110 struct rtc_pll_info pll; in rtc_ioctl() local
115 if (!mach_get_rtc_pll || mach_get_rtc_pll(&pll)) in rtc_ioctl()
117 return copy_to_user(argp, &pll, sizeof pll) ? -EFAULT : 0; in rtc_ioctl()
124 if (copy_from_user(&pll, argp, sizeof(pll))) in rtc_ioctl()
126 return mach_set_rtc_pll(&pll); in rtc_ioctl()
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| /arch/c6x/platforms/ |
| D | plldata.c | 170 struct pll_data *pll = &c6x_soc_pll1; in c6455_setup_clocks() local
171 struct clk *sysclks = pll->sysclks; in c6455_setup_clocks()
173 pll->flags = PLL_HAS_PRE | PLL_HAS_MUL; in c6455_setup_clocks()
208 struct pll_data *pll = &c6x_soc_pll1; in c6457_setup_clocks() local
209 struct clk *sysclks = pll->sysclks; in c6457_setup_clocks()
211 pll->flags = PLL_HAS_MUL | PLL_HAS_POST; in c6457_setup_clocks()
258 struct pll_data *pll = &c6x_soc_pll1; in c6472_setup_clocks() local
259 struct clk *sysclks = pll->sysclks; in c6472_setup_clocks()
262 pll->flags = PLL_HAS_MUL; in c6472_setup_clocks()
307 struct pll_data *pll = &c6x_soc_pll1; in c6474_setup_clocks() local
[all …]
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| D | pll.c | 200 static u32 pll_read(struct pll_data *pll, int reg) in pll_read() argument
202 return soc_readl(pll->base + reg); in pll_read()
208 struct pll_data *pll; in clk_sysclk_recalc() local
220 pll = clk->parent->pll_data; in clk_sysclk_recalc()
224 rate = pll->input_rate; in clk_sysclk_recalc()
239 v = pll_read(pll, clk->div); in clk_sysclk_recalc()
269 struct pll_data *pll = clk->pll_data; in clk_pllclk_recalc() local
275 ctrl = pll_read(pll, PLLCTL); in clk_pllclk_recalc()
276 rate = pll->input_rate = clk->parent->rate; in clk_pllclk_recalc()
283 if (pll->flags & PLL_HAS_MUL) { in clk_pllclk_recalc()
[all …]
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| /arch/mips/boot/dts/qca/ |
| D | ar9331.dtsi | 17 clocks = <&pll ATH79_CLK_CPU>;
90 pll: pll-controller@18050000 { label
91 compatible = "qca,ar9330-pll";
126 clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
139 clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
162 clocks = <&pll ATH79_CLK_AHB>;
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| D | ar9132.dtsi | 17 clocks = <&pll ATH79_CLK_CPU>;
64 clocks = <&pll ATH79_CLK_AHB>;
89 pll: pll-controller@18050000 { label
90 compatible = "qca,ar9132-pll",
91 "qca,ar9130-pll";
107 clocks = <&pll ATH79_CLK_AHB>;
151 clocks = <&pll ATH79_CLK_AHB>;
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| /arch/c6x/boot/dts/ |
| D | tms320c6457.dtsi | 62 compatible = "ti,c6457-pll", "ti,c64x+pll";
64 ti,c64x+pll-bypass-delay = <300>;
65 ti,c64x+pll-reset-delay = <24000>;
66 ti,c64x+pll-lock-delay = <50000>;
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| D | tms320c6474.dtsi | 83 compatible = "ti,c6474-pll", "ti,c64x+pll";
85 ti,c64x+pll-bypass-delay = <120>;
86 ti,c64x+pll-reset-delay = <30000>;
87 ti,c64x+pll-lock-delay = <60000>;
|
| D | tms320c6455.dtsi | 72 compatible = "ti,c6455-pll", "ti,c64x+pll";
74 ti,c64x+pll-bypass-delay = <1440>;
75 ti,c64x+pll-reset-delay = <15360>;
76 ti,c64x+pll-lock-delay = <24000>;
|
| D | tms320c6472.dtsi | 106 compatible = "ti,c6472-pll", "ti,c64x+pll";
108 ti,c64x+pll-bypass-delay = <200>;
109 ti,c64x+pll-reset-delay = <12000>;
110 ti,c64x+pll-lock-delay = <80000>;
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| D | tms320c6678.dtsi | 128 compatible = "ti,c6678-pll", "ti,c64x+pll";
130 ti,c64x+pll-bypass-delay = <200>;
131 ti,c64x+pll-reset-delay = <12000>;
132 ti,c64x+pll-lock-delay = <80000>;
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| /arch/arm/boot/dts/ |
| D | keystone-k2e-clocks.dtsi | 11 compatible = "ti,keystone,main-pll-clock";
19 compatible = "ti,keystone,pll-clock";
28 compatible = "ti,keystone,pll-clock";
30 clock-output-names = "ddr-3a-pll-clk";
|
| D | wm8850.dtsi | 90 compatible = "wm,wm8850-pll-clock";
97 compatible = "wm,wm8850-pll-clock";
104 compatible = "wm,wm8850-pll-clock";
111 compatible = "wm,wm8850-pll-clock";
118 compatible = "wm,wm8850-pll-clock";
125 compatible = "wm,wm8850-pll-clock";
132 compatible = "wm,wm8850-pll-clock";
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| D | wm8650.dtsi | 87 compatible = "wm,wm8650-pll-clock";
94 compatible = "wm,wm8650-pll-clock";
101 compatible = "wm,wm8650-pll-clock";
108 compatible = "wm,wm8650-pll-clock";
115 compatible = "wm,wm8650-pll-clock";
|
| D | dove-cubox.dts | 102 silabs,pll-source = <0 0>, <1 0>;
109 silabs,pll-master;
117 silabs,pll-master;
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| D | keystone-k2l-clocks.dtsi | 11 compatible = "ti,keystone,pll-clock";
13 clock-output-names = "arm-pll-clk";
20 compatible = "ti,keystone,main-pll-clock";
28 compatible = "ti,keystone,pll-clock";
37 compatible = "ti,keystone,pll-clock";
39 clock-output-names = "ddr-3a-pll-clk";
|
| D | stih410-clock.dtsi | 37 clockgen_a9_pll: clockgen-a9-pll {
43 clock-output-names = "clockgen-a9-pll-odf";
75 clk_s_a0_pll: clk-s-a0-pll {
81 clock-output-names = "clk-s-a0-pll-ofd-0";
82 clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
101 compatible = "st,quadfs-pll";
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| D | stih407-clock.dtsi | 34 clockgen_a9_pll: clockgen-a9-pll {
40 clock-output-names = "clockgen-a9-pll-odf";
75 clk_s_a0_pll: clk-s-a0-pll {
81 clock-output-names = "clk-s-a0-pll-ofd-0";
82 clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
100 compatible = "st,quadfs-pll";
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| /arch/mips/ar7/ |
| D | clock.c | 49 u32 pll; member
165 u32 pll = readl(&clock->pll); in tnetd7300_get_clock() local
169 int mul = ((pll & MUL_MASK) >> MUL_SHIFT) + 1; in tnetd7300_get_clock()
189 if ((pll & PLL_MODE_MASK) == 0) in tnetd7300_get_clock()
192 if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) { in tnetd7300_get_clock()
230 writel(4, &clock->pll); in tnetd7300_set_clock()
231 while (readl(&clock->pll) & PLL_STATUS) in tnetd7300_set_clock()
233 writel(((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e, &clock->pll); in tnetd7300_set_clock()
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| /arch/arm64/boot/dts/nvidia/ |
| D | tegra210-p2371-2180.dts | 14 avdd-pll-uerefe-supply = <&avdd_1v05_pll>;
17 dvdd-pex-pll-supply = <&vdd_pex_1v05>;
18 hvdd-pex-pll-e-supply = <&vdd_1v8>;
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| D | tegra210-p3450-0000.dts | 33 avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
36 dvdd-pex-pll-supply = <&vdd_pex_1v05>;
37 hvdd-pex-pll-e-supply = <&vdd_1v8>;
71 vdd-pll-supply = <&vdd_1v8>;
404 avdd-pll-utmip-supply = <&vdd_1v8>;
405 avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
406 dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>;
407 hvdd-usb-ss-pll-e-supply = <&vdd_1v8>;
415 avdd-pll-utmip-supply = <&vdd_1v8>;
416 avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
[all …]
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| D | tegra186-p2771-0000.dts | 108 avdd-pll-erefeut-supply = <&vdd_1v8_pll>;
111 dvdd-pex-pll-supply = <&vdd_pex>;
113 hvdd-pex-pll-supply = <&vdd_1v8>;
209 hvdd-pex-pll-supply = <&vdd_1v8>;
254 vdd-pll-supply = <&vdd_1v8_ap>;
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| /arch/arm64/boot/dts/sprd/ |
| D | sc9860.dtsi | 195 pll: pll { label
196 compatible = "sprd,sc9860-pll";
205 clocks = <&ext_26m>, <&pll 0>,
213 clocks = <&ext_26m>, <&pll 0>,
235 clocks = <&ext_26m>, <&pll 0>;
249 clocks = <&pll 0>;
256 clocks = <&ext_26m>, <&pll 0>;
270 clocks = <&ext_26m>, <&pll 0>;
284 clocks = <&ext_26m>, <&pll 0>;
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| /arch/arm/mach-s3c24xx/ |
| D | Makefile | 13 obj-$(CONFIG_S3C2410_PLL) += pll-s3c2410.o
26 obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o
27 obj-$(CONFIG_S3C2440_PLL_16934400) += pll-s3c2440-16934400.o
|