Searched refs:pll0 (Results 1 – 11 of 11) sorted by relevance
| /arch/arc/boot/dts/ |
| D | abilis_tb10x.dtsi | 48 pll0: oscillator { label
51 clock-output-names = "pll0";
56 clocks = <&pll0>;
62 clocks = <&pll0>;
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| D | abilis_tb100.dtsi | 17 pll0: oscillator { label
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| D | abilis_tb101.dtsi | 17 pll0: oscillator { label
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| /arch/arm/boot/dts/ |
| D | stih410-clock.dtsi | 77 compatible = "st,clkgen-pll0";
117 clk_s_c0_pll0: clk-s-c0-pll0 {
119 compatible = "st,clkgen-pll0";
123 clock-output-names = "clk-s-c0-pll0-odf-0";
124 clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
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| D | stih407-clock.dtsi | 77 compatible = "st,clkgen-pll0";
116 clk_s_c0_pll0: clk-s-c0-pll0 {
118 compatible = "st,clkgen-pll0";
122 clock-output-names = "clk-s-c0-pll0-odf-0";
123 clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
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| D | stih418-clock.dtsi | 78 compatible = "st,clkgen-pll0";
115 clk_s_c0_pll0: clk-s-c0-pll0 {
117 compatible = "st,clkgen-pll0";
121 clock-output-names = "clk-s-c0-pll0-odf-0";
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| D | dove-cubox.dts | 101 /* connect xtal input as source of pll0 and pll1 */
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| D | da850.dtsi | 135 pll0: clock-controller@11000 { label
136 compatible = "ti,da850-pll0";
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| D | r8a73a4.dtsi | 528 clock-output-names = "main", "pll0", "pll1", "pll2",
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| D | sh73a0.dtsi | 637 clock-output-names = "main", "pll0", "pll1", "pll2",
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| /arch/arm/mach-davinci/ |
| D | da850.c | 650 void __iomem *pll0; in da850_init_time() local
657 pll0 = ioremap(DA8XX_PLL0_BASE, SZ_4K); in da850_init_time()
660 da850_pll0_init(NULL, pll0, cfgchip); in da850_init_time()
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