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Searched refs:srs (Results 1 – 3 of 3) sorted by relevance

/arch/powerpc/kvm/
Dmpic.c945 int srs, ibs; in openpic_msi_write() local
953 srs = val >> MSIIR_SRS_SHIFT; in openpic_msi_write()
954 idx += srs; in openpic_msi_write()
956 opp->msi[srs].msir |= 1 << ibs; in openpic_msi_write()
971 int i, srs; in openpic_msi_read() local
977 srs = addr >> 4; in openpic_msi_read()
988 r = opp->msi[srs].msir; in openpic_msi_read()
990 opp->msi[srs].msir = 0; in openpic_msi_read()
991 openpic_set_irq(opp, opp->irq_msi + srs, 0); in openpic_msi_read()
/arch/powerpc/sysdev/
Dfsl_msi.c69 int cascade_virq, srs; in fsl_msi_print_chip() local
71 srs = (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK; in fsl_msi_print_chip()
72 cascade_virq = msi_data->cascade_array[srs]->virq; in fsl_msi_print_chip()
/arch/mips/kernel/
Dtraps.c1987 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) in set_vi_srs_handler() argument
1999 srs = 0; in set_vi_srs_handler()
2006 if (srs >= srssets) in set_vi_srs_handler()
2007 panic("Shadow register set %d not supported", srs); in set_vi_srs_handler()
2011 board_bind_eic_interrupt(n, srs); in set_vi_srs_handler()
2015 change_c0_srsmap(0xf << n*4, srs << n*4); in set_vi_srs_handler()
2018 if (srs == 0) { in set_vi_srs_handler()