Searched refs:stores (Results 1 – 25 of 27) sorted by relevance
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| /arch/sparc/kernel/ |
| D | dtlb_prot.S | 20 membar #Sync ! Synchronize stores
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| /arch/mips/include/asm/ |
| D | mips-r2-to-r6-emul.h | 23 u64 stores; member
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| D | fpu_emulator.h | 27 unsigned long stores; member
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| /arch/c6x/lib/ |
| D | divi.S | 23 ;; call to divu. It stores B3 in on the stack.
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| D | remi.S | 23 ;; call to divu. It stores B3 in on the stack.
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| D | remu.S | 23 ;; call to divu. It stores B3 in on the stack.
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| D | divu.S | 23 ;; call to divu. It stores B3 in on the stack.
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| /arch/sparc/lib/ |
| D | M7memset.S | 167 ! Use long word stores.
179 and %o2, 63, %o3 ! %o3 = bytes left after blk stores.
187 ! initial cache-clearing stores
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| D | M7memcpy.S | 434 ! lines from memory. Use ST_CHUNK stores to first element of each cache
437 ! Initial stores using MRU version of BIS to keep cache line in
444 ! We use STORE_MRU_ASI for the first seven stores to each cache line
452 ! the store miss buffer. Then the matching stores for all those
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| /arch/mips/kernel/ |
| D | mips-r2-to-r6-emul.c | 1418 MIPS_R2_STATS(stores); in mipsr2_decoder()
1488 MIPS_R2_STATS(stores); in mipsr2_decoder()
1845 MIPS_R2_STATS(stores); in mipsr2_decoder()
1963 MIPS_R2_STATS(stores); in mipsr2_decoder()
2270 (unsigned long)__this_cpu_read(mipsr2emustats.stores), in mipsr2_emul_show()
2271 (unsigned long)__this_cpu_read(mipsr2bdemustats.stores)); in mipsr2_emul_show()
2326 __this_cpu_write((mipsr2emustats).stores, 0); in mipsr2_clear_show()
2327 __this_cpu_write((mipsr2bdemustats).stores, 0); in mipsr2_clear_show()
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| /arch/h8300/lib/ |
| D | udivsi3.S | 4 ;; This function also computes the remainder and stores it in er3.
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| /arch/powerpc/lib/ |
| D | memcpy_64.S | 115 ld r9,0(r4) # 3+2n loads, 2+2n stores
127 0: ld r0,0(r4) # 4+2n loads, 3+2n stores
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| /arch/mips/math-emu/ |
| D | me-debugfs.c | 56 __this_cpu_write((fpuemustats).stores, 0); in fpuemustats_clear_show()
211 FPU_STAT_CREATE(stores); in debugfs_fpuemu()
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| D | cp1emu.c | 1070 MIPS_FPU_EMU_INC_STATS(stores); in cop1Emulate()
1104 MIPS_FPU_EMU_INC_STATS(stores); in cop1Emulate()
1501 MIPS_FPU_EMU_INC_STATS(stores); in fpux_emu()
1598 MIPS_FPU_EMU_INC_STATS(stores); in fpux_emu()
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| /arch/nds32/kernel/ |
| D | ex-exit.S | 184 beqz $r6, 1f ! r6 stores fn for kernel thread
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| /arch/arm/crypto/ |
| D | aes-ce-core.S | 328 vst1.8 {q2}, [r4] @ overlapping stores
366 vst1.8 {q1}, [r4] @ overlapping stores
584 vst1.8 {q2}, [r4] @ overlapping stores
676 vst1.8 {q2}, [r4] @ overlapping stores
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| /arch/alpha/lib/ |
| D | ev6-copy_user.S | 64 EXI( ldbu $1,0($17) ) # .. .. .. L : Keep loads separate from stores
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| /arch/powerpc/perf/ |
| D | power8-pmu.c | 146 CACHE_EVENT_ATTR(LLC-stores, PM_L2_ST);
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| D | power9-pmu.c | 161 GENERIC_EVENT_ATTR(mem-stores, MEM_STORES);
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| /arch/m68k/fpsp040/ |
| D | x_operr.S | 243 | This routine stores the data in d0, for the given size in d1,
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| /arch/arm/ |
| D | Kconfig | 1081 and Device/Strongly-Ordered loads and stores might cause deadlock
1092 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1098 stores from GroupA and stores from GroupB.
1642 memory write throughput than a sequence of individual 32bit stores.
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| /arch/x86/ |
| D | Kconfig.cpu | 204 stores for this CPU, which can increase performance of some
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| /arch/x86/events/intel/ |
| D | core.c | 277 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
4233 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
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| /arch/x86/crypto/ |
| D | aesni-intel_asm.S | 566 # Reads DLEN bytes starting at DPTR and stores in XMMDst
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| /arch/arm64/ |
| D | Kconfig | 1159 This enables mitigation of the bypassing of previous stores
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