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/arch/arc/mm/
Dcache.c32 unsigned long sz, const int op, const int full_page);
34 void (*__dma_cache_wback_inv)(phys_addr_t start, unsigned long sz);
35 void (*__dma_cache_inv)(phys_addr_t start, unsigned long sz);
36 void (*__dma_cache_wback)(phys_addr_t start, unsigned long sz);
82 unsigned int pad:24, way:2, lsz:2, sz:4; in read_decode_cache_bcr_arcv2() member
84 unsigned int sz:4, lsz:2, way:2, pad:24; in read_decode_cache_bcr_arcv2()
108 p_slc->sz_k = 128 << slc_cfg.sz; in read_decode_cache_bcr_arcv2()
148 unsigned int pad:12, line_len:4, sz:4, config:4, ver:8; in read_decode_cache_bcr() member
150 unsigned int ver:8, config:4, sz:4, line_len:4, pad:12; in read_decode_cache_bcr()
168 p_ic->sz_k = 1 << (ibcr.sz - 1); in read_decode_cache_bcr()
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/arch/mips/include/asm/
Dmips-cps.h22 #define CPS_ACCESSOR_R(unit, sz, name) \ argument
23 static inline uint##sz##_t read_##unit##_##name(void) \
27 switch (sz) { \
45 #define CPS_ACCESSOR_W(unit, sz, name) \ argument
46 static inline void write_##unit##_##name(uint##sz##_t val) \
48 switch (sz) { \
70 #define CPS_ACCESSOR_M(unit, sz, name) \ argument
71 static inline void change_##unit##_##name(uint##sz##_t mask, \
72 uint##sz##_t val) \
74 uint##sz##_t reg_val = read_##unit##_##name(); \
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Dmips-gic.h30 #define GIC_ACCESSOR_RO(sz, off, name) \ argument
31 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_SHARED_OFS + off, name)
34 #define GIC_ACCESSOR_RW(sz, off, name) \ argument
35 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_SHARED_OFS + off, name)
38 #define GIC_VX_ACCESSOR_RO(sz, off, name) \ argument
39 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_LOCAL_OFS + off, vl_##name) \
40 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name)
43 #define GIC_VX_ACCESSOR_RW(sz, off, name) \ argument
44 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_LOCAL_OFS + off, vl_##name) \
45 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name)
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Dmips-cpc.h64 #define CPC_ACCESSOR_RO(sz, off, name) \ argument
65 CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_GCB_OFS + off, name) \
66 CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_COCB_OFS + off, redir_##name)
68 #define CPC_ACCESSOR_RW(sz, off, name) \ argument
69 CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_GCB_OFS + off, name) \
70 CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_COCB_OFS + off, redir_##name)
72 #define CPC_CX_ACCESSOR_RO(sz, off, name) \ argument
73 CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_CLCB_OFS + off, cl_##name) \
74 CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_COCB_OFS + off, co_##name)
76 #define CPC_CX_ACCESSOR_RW(sz, off, name) \ argument
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Dmips-cm.h114 #define GCR_ACCESSOR_RO(sz, off, name) \ argument
115 CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_GCB_OFS + off, name) \
116 CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, redir_##name)
118 #define GCR_ACCESSOR_RW(sz, off, name) \ argument
119 CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_GCB_OFS + off, name) \
120 CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_COCB_OFS + off, redir_##name)
122 #define GCR_CX_ACCESSOR_RO(sz, off, name) \ argument
123 CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name) \
124 CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name)
126 #define GCR_CX_ACCESSOR_RW(sz, off, name) \ argument
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/arch/xtensa/kernel/
Djump_label.c29 size_t sz; member
33 static void local_patch_text(unsigned long addr, const void *data, size_t sz) in local_patch_text() argument
35 memcpy((void *)addr, data, sz); in local_patch_text()
36 local_flush_icache_range(addr, addr + sz); in local_patch_text()
44 local_patch_text(patch->addr, patch->data, patch->sz); in patch_text_stop_machine()
49 __invalidate_icache_range(patch->addr, patch->sz); in patch_text_stop_machine()
54 static void patch_text(unsigned long addr, const void *data, size_t sz) in patch_text() argument
60 .sz = sz, in patch_text()
69 local_patch_text(addr, data, sz); in patch_text()
/arch/arm/include/asm/
Dbitops.h200 #define find_first_zero_bit(p,sz) _find_first_zero_bit_le(p,sz) argument
201 #define find_next_zero_bit(p,sz,off) _find_next_zero_bit_le(p,sz,off) argument
202 #define find_first_bit(p,sz) _find_first_bit_le(p,sz) argument
203 #define find_next_bit(p,sz,off) _find_next_bit_le(p,sz,off) argument
209 #define find_first_zero_bit(p,sz) _find_first_zero_bit_be(p,sz) argument
210 #define find_next_zero_bit(p,sz,off) _find_next_zero_bit_be(p,sz,off) argument
211 #define find_first_bit(p,sz) _find_first_bit_be(p,sz) argument
212 #define find_next_bit(p,sz,off) _find_next_bit_be(p,sz,off) argument
/arch/arm64/include/asm/
Dpercpu.h40 #define PERCPU_RW_OPS(sz) \ argument
41 static inline unsigned long __percpu_read_##sz(void *ptr) \
43 return READ_ONCE(*(u##sz *)ptr); \
46 static inline void __percpu_write_##sz(void *ptr, unsigned long val) \
48 WRITE_ONCE(*(u##sz *)ptr, (u##sz)val); \
51 #define __PERCPU_OP_CASE(w, sfx, name, sz, op_llsc, op_lse) \ argument
53 __percpu_##name##_case_##sz(void *ptr, unsigned long val) \
56 u##sz tmp; \
68 [ptr] "+Q"(*(u##sz *)ptr) \
69 : [val] "r" ((u##sz)(val))); \
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Dcmpxchg.h21 #define __XCHG_CASE(w, sfx, name, sz, mb, nop_lse, acq, acq_lse, rel, cl) \ argument
22 static inline u##sz __xchg_case_##name##sz(u##sz x, volatile void *ptr) \
24 u##sz ret; \
38 : "=&r" (ret), "=&r" (tmp), "+Q" (*(u##sz *)ptr) \
106 #define __CMPXCHG_CASE(name, sz) \ argument
107 static inline u##sz __cmpxchg_case_##name##sz(volatile void *ptr, \
108 u##sz old, \
109 u##sz new) \
111 return __lse_ll_sc_body(_cmpxchg_case_##name##sz, \
232 #define __CMPWAIT_CASE(w, sfx, sz) \ argument
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Datomic_ll_sc.h239 #define __CMPXCHG_CASE(w, sfx, name, sz, mb, acq, rel, cl, constraint) \ argument
240 static inline u##sz \
241 __ll_sc__cmpxchg_case_##name##sz(volatile void *ptr, \
243 u##sz new) \
246 u##sz oldval; \
253 if (sz < 32) \
254 old = (u##sz)old; \
266 [v] "+Q" (*(u##sz *)ptr) \
/arch/arm64/crypto/
Daes-cipher-core.S20 .macro __pair1, sz, op, reg0, reg1, in0, in1e, in1d, shift
49 .macro __pair0, sz, op, reg0, reg1, in0, in1e, in1d, shift
52 ldr\op \reg0, [tt, \reg0, uxtw #\sz]
53 ldr\op \reg1, [tt, \reg1, uxtw #\sz]
56 .macro __hround, out0, out1, in0, in1, in2, in3, t0, t1, enc, sz, op
59 __pair\enc \sz, \op, w12, w13, \in0, \in1, \in3, 0
60 __pair\enc \sz, \op, w14, w15, \in1, \in2, \in0, 8
61 __pair\enc \sz, \op, w16, w17, \in2, \in3, \in1, 16
62 __pair\enc \sz, \op, \t0, \t1, \in3, \in0, \in2, 24
74 .macro fround, out0, out1, out2, out3, in0, in1, in2, in3, sz=2, op argument
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/arch/arm/mach-orion5x/
Dts78xx-setup.c160 int sz; in ts78xx_ts_nand_write_buf() local
163 sz = min_t(int, 4 - off, len); in ts78xx_ts_nand_write_buf()
164 writesb(io_base, buf, sz); in ts78xx_ts_nand_write_buf()
165 buf += sz; in ts78xx_ts_nand_write_buf()
166 len -= sz; in ts78xx_ts_nand_write_buf()
169 sz = len >> 2; in ts78xx_ts_nand_write_buf()
170 if (sz) { in ts78xx_ts_nand_write_buf()
172 writesl(io_base, buf32, sz); in ts78xx_ts_nand_write_buf()
173 buf += sz << 2; in ts78xx_ts_nand_write_buf()
174 len -= sz << 2; in ts78xx_ts_nand_write_buf()
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/arch/arm/crypto/
Daes-cipher-core.S34 .macro __load, out, in, idx, sz, op
36 ldr\op \out, [ttab, \in, lsr #(8 * \idx) - \sz]
38 ldr\op \out, [ttab, \in, lsl #\sz]
42 .macro __hround, out0, out1, in0, in1, in2, in3, t3, t4, enc, sz, op, oldcpsr
45 __load \out0, \out0, 0, \sz, \op
46 __load t0, t0, 1, \sz, \op
55 __load \out1, \out1, 0, \sz, \op
57 __load t1, t1, 1, \sz, \op
58 __load t2, t2, 2, \sz, \op
70 __load \t3, \t3, 2, \sz, \op
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/arch/arm64/kernel/
Dsys32.c24 compat_size_t, sz, struct compat_statfs64 __user *, buf) in COMPAT_SYSCALL_DEFINE3() argument
35 if (sz == 88) in COMPAT_SYSCALL_DEFINE3()
36 sz = 84; in COMPAT_SYSCALL_DEFINE3()
38 return kcompat_sys_statfs64(pathname, sz, buf); in COMPAT_SYSCALL_DEFINE3()
41 COMPAT_SYSCALL_DEFINE3(aarch32_fstatfs64, unsigned int, fd, compat_size_t, sz, in COMPAT_SYSCALL_DEFINE3() argument
45 if (sz == 88) in COMPAT_SYSCALL_DEFINE3()
46 sz = 84; in COMPAT_SYSCALL_DEFINE3()
48 return kcompat_sys_fstatfs64(fd, sz, buf); in COMPAT_SYSCALL_DEFINE3()
/arch/arm64/mm/
Dhugetlbpage.c205 pte_t *ptep, pte_t pte, unsigned long sz) in set_huge_swap_pte_at() argument
210 ncontig = num_contig_ptes(sz, &pgsize); in set_huge_swap_pte_at()
217 unsigned long addr, unsigned long sz) in huge_pte_alloc() argument
229 if (sz == PUD_SIZE) { in huge_pte_alloc()
231 } else if (sz == (CONT_PTE_SIZE)) { in huge_pte_alloc()
236 WARN_ON(addr & (sz - 1)); in huge_pte_alloc()
245 } else if (sz == PMD_SIZE) { in huge_pte_alloc()
251 } else if (sz == (CONT_PMD_SIZE)) { in huge_pte_alloc()
253 WARN_ON(addr & (sz - 1)); in huge_pte_alloc()
261 unsigned long addr, unsigned long sz) in huge_pte_offset() argument
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/arch/powerpc/platforms/cell/spufs/
Dcoredump.c42 int i, sz, total = 0; in spufs_ctx_note_size() local
48 sz = spufs_coredump_read[i].size; in spufs_ctx_note_size()
54 total += roundup(sz, 4); in spufs_ctx_note_size()
122 int sz, rc, total = 0; in spufs_arch_write_note() local
134 sz = spufs_coredump_read[i].size; in spufs_arch_write_note()
138 en.n_descsz = sz; in spufs_arch_write_note()
157 } while (rc == bufsz && total < sz); in spufs_arch_write_note()
162 skip = roundup(cprm->pos - total + sz, 4) - cprm->pos; in spufs_arch_write_note()
/arch/sparc/include/asm/
Dio_32.h10 #define memset_io(d,c,sz) _memset_io(d,c,sz) argument
11 #define memcpy_fromio(d,s,sz) _memcpy_fromio(d,s,sz) argument
12 #define memcpy_toio(d,s,sz) _memcpy_toio(d,s,sz) argument
/arch/arm/mach-ebsa110/include/mach/
Dio.h63 extern void insb(unsigned int port, void *buf, int sz);
65 extern void insw(unsigned int port, void *buf, int sz);
67 extern void insl(unsigned int port, void *buf, int sz);
70 extern void outsb(unsigned int port, const void *buf, int sz);
72 extern void outsw(unsigned int port, const void *buf, int sz);
74 extern void outsl(unsigned int port, const void *buf, int sz);
/arch/arc/include/asm/
Duaccess.h50 #define __user_ok(addr, sz) (((sz) <= TASK_SIZE) && \ argument
51 ((addr) <= (get_fs() - (sz))))
52 #define __access_ok(addr, sz) (unlikely(__kernel_ok) || \ argument
53 likely(__user_ok((addr), (sz))))
57 #define __get_user_fn(sz, u, k) \ argument
60 switch (sz) { \
118 #define __put_user_fn(sz, u, k) \ argument
121 switch (sz) { \
Dcacheflush.h40 void dma_cache_wback_inv(phys_addr_t start, unsigned long sz);
41 void dma_cache_inv(phys_addr_t start, unsigned long sz);
42 void dma_cache_wback(phys_addr_t start, unsigned long sz);
Dio.h37 #define ioremap_nocache(phy, sz) ioremap(phy, sz) argument
38 #define ioremap_wc(phy, sz) ioremap(phy, sz) argument
39 #define ioremap_wt(phy, sz) ioremap(phy, sz) argument
/arch/arm/mach-s3c24xx/include/mach/
Dio.h36 #define DECLARE_DYN_OUT(sz,fnsuffix,instr) \ argument
51 #define DECLARE_DYN_IN(sz,fnsuffix,instr) \ argument
52 static inline unsigned sz __in##fnsuffix (unsigned int port) \
63 return (unsigned sz)value; \
71 #define DECLARE_IO(sz,fnsuffix,instr) \ argument
72 DECLARE_DYN_IN(sz,fnsuffix,instr) \
73 DECLARE_DYN_OUT(sz,fnsuffix,instr)
/arch/x86/boot/tools/
Dbuild.c334 unsigned int i, sz, setup_sectors, init_sz; in main() local
388 sz = sb.st_size; in main()
389 printf("System is %d kB\n", (sz+1023)/1024); in main()
390 kernel = mmap(NULL, sz, PROT_READ, MAP_SHARED, fd, 0); in main()
394 sys_size = (sz + 15 + 4) / 16; in main()
418 crc = partial_crc32(kernel, sz, crc); in main()
419 if (fwrite(kernel, 1, sz, dest) != sz) in main()
423 while (sz++ < (sys_size*16) - 4) { in main()
/arch/arc/kernel/
Dsetup.c74 cpu->iccm.sz = 4096 << iccm.sz; /* 8K to 512K */ in read_decode_ccm_bcr()
81 cpu->dccm.sz = 2048 << dccm.sz; /* 2K to 256K */ in read_decode_ccm_bcr()
93 cpu->iccm.sz = 256 << iccm.sz00; /* 512B to 16M */ in read_decode_ccm_bcr()
95 cpu->iccm.sz <<= iccm.sz01; in read_decode_ccm_bcr()
103 cpu->dccm.sz = 256 << dccm.sz0; in read_decode_ccm_bcr()
105 cpu->dccm.sz <<= dccm.sz1; in read_decode_ccm_bcr()
367 if (cpu->dccm.sz || cpu->iccm.sz) in arc_extn_mumbojumbo()
369 cpu->dccm.base_addr, TO_KB(cpu->dccm.sz), in arc_extn_mumbojumbo()
370 cpu->iccm.base_addr, TO_KB(cpu->iccm.sz)); in arc_extn_mumbojumbo()
413 if (CONFIG_ARC_DCCM_SZ * SZ_1K != cpu->dccm.sz) in arc_chk_core_config()
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/arch/sh/mm/
Dhugetlbpage.c26 unsigned long addr, unsigned long sz) in huge_pte_alloc() argument
47 unsigned long addr, unsigned long sz) in huge_pte_offset() argument

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