1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __LINUX_OMAP_DMA_H
3 #define __LINUX_OMAP_DMA_H
4 /*
5 * Legacy OMAP DMA handling defines and functions
6 *
7 * NOTE: Do not use these any longer.
8 *
9 * Use the generic dmaengine functions as defined in
10 * include/linux/dmaengine.h.
11 *
12 * Copyright (C) 2003 Nokia Corporation
13 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
14 *
15 */
16
17 #include <linux/platform_device.h>
18
19 #define INT_DMA_LCD (NR_IRQS_LEGACY + 25)
20
21 #define OMAP1_DMA_TOUT_IRQ (1 << 0)
22 #define OMAP_DMA_DROP_IRQ (1 << 1)
23 #define OMAP_DMA_HALF_IRQ (1 << 2)
24 #define OMAP_DMA_FRAME_IRQ (1 << 3)
25 #define OMAP_DMA_LAST_IRQ (1 << 4)
26 #define OMAP_DMA_BLOCK_IRQ (1 << 5)
27 #define OMAP1_DMA_SYNC_IRQ (1 << 6)
28 #define OMAP2_DMA_PKT_IRQ (1 << 7)
29 #define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8)
30 #define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9)
31 #define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10)
32 #define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11)
33
34 #define OMAP_DMA_CCR_EN (1 << 7)
35 #define OMAP_DMA_CCR_RD_ACTIVE (1 << 9)
36 #define OMAP_DMA_CCR_WR_ACTIVE (1 << 10)
37 #define OMAP_DMA_CCR_SEL_SRC_DST_SYNC (1 << 24)
38 #define OMAP_DMA_CCR_BUFFERING_DISABLE (1 << 25)
39
40 #define OMAP_DMA_DATA_TYPE_S8 0x00
41 #define OMAP_DMA_DATA_TYPE_S16 0x01
42 #define OMAP_DMA_DATA_TYPE_S32 0x02
43
44 #define OMAP_DMA_SYNC_ELEMENT 0x00
45 #define OMAP_DMA_SYNC_FRAME 0x01
46 #define OMAP_DMA_SYNC_BLOCK 0x02
47 #define OMAP_DMA_SYNC_PACKET 0x03
48
49 #define OMAP_DMA_DST_SYNC_PREFETCH 0x02
50 #define OMAP_DMA_SRC_SYNC 0x01
51 #define OMAP_DMA_DST_SYNC 0x00
52
53 #define OMAP_DMA_PORT_EMIFF 0x00
54 #define OMAP_DMA_PORT_EMIFS 0x01
55 #define OMAP_DMA_PORT_OCP_T1 0x02
56 #define OMAP_DMA_PORT_TIPB 0x03
57 #define OMAP_DMA_PORT_OCP_T2 0x04
58 #define OMAP_DMA_PORT_MPUI 0x05
59
60 #define OMAP_DMA_AMODE_CONSTANT 0x00
61 #define OMAP_DMA_AMODE_POST_INC 0x01
62 #define OMAP_DMA_AMODE_SINGLE_IDX 0x02
63 #define OMAP_DMA_AMODE_DOUBLE_IDX 0x03
64
65 #define DMA_DEFAULT_FIFO_DEPTH 0x10
66 #define DMA_DEFAULT_ARB_RATE 0x01
67 /* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
68 #define DMA_THREAD_RESERVE_NORM (0x00 << 12) /* Def */
69 #define DMA_THREAD_RESERVE_ONET (0x01 << 12)
70 #define DMA_THREAD_RESERVE_TWOT (0x02 << 12)
71 #define DMA_THREAD_RESERVE_THREET (0x03 << 12)
72 #define DMA_THREAD_FIFO_NONE (0x00 << 14) /* Def */
73 #define DMA_THREAD_FIFO_75 (0x01 << 14)
74 #define DMA_THREAD_FIFO_25 (0x02 << 14)
75 #define DMA_THREAD_FIFO_50 (0x03 << 14)
76
77 /* DMA4_OCP_SYSCONFIG bits */
78 #define DMA_SYSCONFIG_MIDLEMODE_MASK (3 << 12)
79 #define DMA_SYSCONFIG_CLOCKACTIVITY_MASK (3 << 8)
80 #define DMA_SYSCONFIG_EMUFREE (1 << 5)
81 #define DMA_SYSCONFIG_SIDLEMODE_MASK (3 << 3)
82 #define DMA_SYSCONFIG_SOFTRESET (1 << 2)
83 #define DMA_SYSCONFIG_AUTOIDLE (1 << 0)
84
85 #define DMA_SYSCONFIG_MIDLEMODE(n) ((n) << 12)
86 #define DMA_SYSCONFIG_SIDLEMODE(n) ((n) << 3)
87
88 #define DMA_IDLEMODE_SMARTIDLE 0x2
89 #define DMA_IDLEMODE_NO_IDLE 0x1
90 #define DMA_IDLEMODE_FORCE_IDLE 0x0
91
92 /* Chaining modes*/
93 #ifndef CONFIG_ARCH_OMAP1
94 #define OMAP_DMA_STATIC_CHAIN 0x1
95 #define OMAP_DMA_DYNAMIC_CHAIN 0x2
96 #define OMAP_DMA_CHAIN_ACTIVE 0x1
97 #define OMAP_DMA_CHAIN_INACTIVE 0x0
98 #endif
99
100 #define DMA_CH_PRIO_HIGH 0x1
101 #define DMA_CH_PRIO_LOW 0x0 /* Def */
102
103 /* Errata handling */
104 #define IS_DMA_ERRATA(id) (errata & (id))
105 #define SET_DMA_ERRATA(id) (errata |= (id))
106
107 #define DMA_ERRATA_IFRAME_BUFFERING BIT(0x0)
108 #define DMA_ERRATA_PARALLEL_CHANNELS BIT(0x1)
109 #define DMA_ERRATA_i378 BIT(0x2)
110 #define DMA_ERRATA_i541 BIT(0x3)
111 #define DMA_ERRATA_i88 BIT(0x4)
112 #define DMA_ERRATA_3_3 BIT(0x5)
113 #define DMA_ROMCODE_BUG BIT(0x6)
114
115 /* Attributes for OMAP DMA Contrller */
116 #define DMA_LINKED_LCH BIT(0x0)
117 #define GLOBAL_PRIORITY BIT(0x1)
118 #define RESERVE_CHANNEL BIT(0x2)
119 #define IS_CSSA_32 BIT(0x3)
120 #define IS_CDSA_32 BIT(0x4)
121 #define IS_RW_PRIORITY BIT(0x5)
122 #define ENABLE_1510_MODE BIT(0x6)
123 #define SRC_PORT BIT(0x7)
124 #define DST_PORT BIT(0x8)
125 #define SRC_INDEX BIT(0x9)
126 #define DST_INDEX BIT(0xa)
127 #define IS_BURST_ONLY4 BIT(0xb)
128 #define CLEAR_CSR_ON_READ BIT(0xc)
129 #define IS_WORD_16 BIT(0xd)
130 #define ENABLE_16XX_MODE BIT(0xe)
131 #define HS_CHANNELS_RESERVED BIT(0xf)
132 #define DMA_ENGINE_HANDLE_IRQ BIT(0x10)
133
134 /* Defines for DMA Capabilities */
135 #define DMA_HAS_TRANSPARENT_CAPS (0x1 << 18)
136 #define DMA_HAS_CONSTANT_FILL_CAPS (0x1 << 19)
137 #define DMA_HAS_DESCRIPTOR_CAPS (0x3 << 20)
138
139 enum omap_reg_offsets {
140
141 GCR, GSCR, GRST1, HW_ID,
142 PCH2_ID, PCH0_ID, PCH1_ID, PCHG_ID,
143 PCHD_ID, CAPS_0, CAPS_1, CAPS_2,
144 CAPS_3, CAPS_4, PCH2_SR, PCH0_SR,
145 PCH1_SR, PCHD_SR, REVISION, IRQSTATUS_L0,
146 IRQSTATUS_L1, IRQSTATUS_L2, IRQSTATUS_L3, IRQENABLE_L0,
147 IRQENABLE_L1, IRQENABLE_L2, IRQENABLE_L3, SYSSTATUS,
148 OCP_SYSCONFIG,
149
150 /* omap1+ specific */
151 CPC, CCR2, LCH_CTRL,
152
153 /* Common registers for all omap's */
154 CSDP, CCR, CICR, CSR,
155 CEN, CFN, CSFI, CSEI,
156 CSAC, CDAC, CDEI,
157 CDFI, CLNK_CTRL,
158
159 /* Channel specific registers */
160 CSSA, CDSA, COLOR,
161 CCEN, CCFN,
162
163 /* omap3630 and omap4 specific */
164 CDP, CNDP, CCDN,
165
166 };
167
168 enum omap_dma_burst_mode {
169 OMAP_DMA_DATA_BURST_DIS = 0,
170 OMAP_DMA_DATA_BURST_4,
171 OMAP_DMA_DATA_BURST_8,
172 OMAP_DMA_DATA_BURST_16,
173 };
174
175 enum end_type {
176 OMAP_DMA_LITTLE_ENDIAN = 0,
177 OMAP_DMA_BIG_ENDIAN
178 };
179
180 enum omap_dma_color_mode {
181 OMAP_DMA_COLOR_DIS = 0,
182 OMAP_DMA_CONSTANT_FILL,
183 OMAP_DMA_TRANSPARENT_COPY
184 };
185
186 enum omap_dma_write_mode {
187 OMAP_DMA_WRITE_NON_POSTED = 0,
188 OMAP_DMA_WRITE_POSTED,
189 OMAP_DMA_WRITE_LAST_NON_POSTED
190 };
191
192 enum omap_dma_channel_mode {
193 OMAP_DMA_LCH_2D = 0,
194 OMAP_DMA_LCH_G,
195 OMAP_DMA_LCH_P,
196 OMAP_DMA_LCH_PD
197 };
198
199 struct omap_dma_channel_params {
200 int data_type; /* data type 8,16,32 */
201 int elem_count; /* number of elements in a frame */
202 int frame_count; /* number of frames in a element */
203
204 int src_port; /* Only on OMAP1 REVISIT: Is this needed? */
205 int src_amode; /* constant, post increment, indexed,
206 double indexed */
207 unsigned long src_start; /* source address : physical */
208 int src_ei; /* source element index */
209 int src_fi; /* source frame index */
210
211 int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */
212 int dst_amode; /* constant, post increment, indexed,
213 double indexed */
214 unsigned long dst_start; /* source address : physical */
215 int dst_ei; /* source element index */
216 int dst_fi; /* source frame index */
217
218 int trigger; /* trigger attached if the channel is
219 synchronized */
220 int sync_mode; /* sycn on element, frame , block or packet */
221 int src_or_dst_synch; /* source synch(1) or destination synch(0) */
222
223 int ie; /* interrupt enabled */
224
225 unsigned char read_prio;/* read priority */
226 unsigned char write_prio;/* write priority */
227
228 #ifndef CONFIG_ARCH_OMAP1
229 enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
230 #endif
231 };
232
233 struct omap_dma_lch {
234 int next_lch;
235 int dev_id;
236 u16 saved_csr;
237 u16 enabled_irqs;
238 const char *dev_name;
239 void (*callback)(int lch, u16 ch_status, void *data);
240 void *data;
241 long flags;
242 /* required for Dynamic chaining */
243 int prev_linked_ch;
244 int next_linked_ch;
245 int state;
246 int chain_id;
247 int status;
248 };
249
250 struct omap_dma_dev_attr {
251 u32 dev_caps;
252 u16 lch_count;
253 u16 chan_count;
254 };
255
256 enum {
257 OMAP_DMA_REG_NONE,
258 OMAP_DMA_REG_16BIT,
259 OMAP_DMA_REG_2X16BIT,
260 OMAP_DMA_REG_32BIT,
261 };
262
263 struct omap_dma_reg {
264 u16 offset;
265 u8 stride;
266 u8 type;
267 };
268
269 #define SDMA_FILTER_PARAM(hw_req) ((int[]) { (hw_req) })
270 struct dma_slave_map;
271
272 /* System DMA platform data structure */
273 struct omap_system_dma_plat_info {
274 const struct omap_dma_reg *reg_map;
275 unsigned channel_stride;
276 struct omap_dma_dev_attr *dma_attr;
277 u32 errata;
278 void (*show_dma_caps)(void);
279 void (*clear_lch_regs)(int lch);
280 void (*clear_dma)(int lch);
281 void (*dma_write)(u32 val, int reg, int lch);
282 u32 (*dma_read)(int reg, int lch);
283
284 const struct dma_slave_map *slave_map;
285 int slavecnt;
286 };
287
288 #ifdef CONFIG_ARCH_OMAP2PLUS
289 #define dma_omap2plus() 1
290 #else
291 #define dma_omap2plus() 0
292 #endif
293 #define dma_omap1() (!dma_omap2plus())
294 #define __dma_omap15xx(d) (dma_omap1() && (d)->dev_caps & ENABLE_1510_MODE)
295 #define __dma_omap16xx(d) (dma_omap1() && (d)->dev_caps & ENABLE_16XX_MODE)
296 #define dma_omap15xx() __dma_omap15xx(d)
297 #define dma_omap16xx() __dma_omap16xx(d)
298
299 #if defined(CONFIG_ARCH_OMAP)
300 extern struct omap_system_dma_plat_info *omap_get_plat_info(void);
301
302 extern void omap_set_dma_priority(int lch, int dst_port, int priority);
303 extern int omap_request_dma(int dev_id, const char *dev_name,
304 void (*callback)(int lch, u16 ch_status, void *data),
305 void *data, int *dma_ch);
306 extern void omap_enable_dma_irq(int ch, u16 irq_bits);
307 extern void omap_disable_dma_irq(int ch, u16 irq_bits);
308 extern void omap_free_dma(int ch);
309 extern void omap_start_dma(int lch);
310 extern void omap_stop_dma(int lch);
311 extern void omap_set_dma_transfer_params(int lch, int data_type,
312 int elem_count, int frame_count,
313 int sync_mode,
314 int dma_trigger, int src_or_dst_synch);
315 extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
316 extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
317
318 extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
319 unsigned long src_start,
320 int src_ei, int src_fi);
321 extern void omap_set_dma_src_data_pack(int lch, int enable);
322 extern void omap_set_dma_src_burst_mode(int lch,
323 enum omap_dma_burst_mode burst_mode);
324
325 extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
326 unsigned long dest_start,
327 int dst_ei, int dst_fi);
328 extern void omap_set_dma_dest_data_pack(int lch, int enable);
329 extern void omap_set_dma_dest_burst_mode(int lch,
330 enum omap_dma_burst_mode burst_mode);
331
332 extern void omap_set_dma_params(int lch,
333 struct omap_dma_channel_params *params);
334
335 extern void omap_dma_link_lch(int lch_head, int lch_queue);
336
337 extern int omap_set_dma_callback(int lch,
338 void (*callback)(int lch, u16 ch_status, void *data),
339 void *data);
340 extern dma_addr_t omap_get_dma_src_pos(int lch);
341 extern dma_addr_t omap_get_dma_dst_pos(int lch);
342 extern int omap_get_dma_active_status(int lch);
343 extern int omap_dma_running(void);
344 extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
345 int tparams);
346 void omap_dma_global_context_save(void);
347 void omap_dma_global_context_restore(void);
348
349 #if defined(CONFIG_ARCH_OMAP1) && IS_ENABLED(CONFIG_FB_OMAP)
350 #include <mach/lcd_dma.h>
351 #else
omap_lcd_dma_running(void)352 static inline int omap_lcd_dma_running(void)
353 {
354 return 0;
355 }
356 #endif
357
358 #else /* CONFIG_ARCH_OMAP */
359
omap_get_plat_info(void)360 static inline struct omap_system_dma_plat_info *omap_get_plat_info(void)
361 {
362 return NULL;
363 }
364
omap_request_dma(int dev_id,const char * dev_name,void (* callback)(int lch,u16 ch_status,void * data),void * data,int * dma_ch)365 static inline int omap_request_dma(int dev_id, const char *dev_name,
366 void (*callback)(int lch, u16 ch_status, void *data),
367 void *data, int *dma_ch)
368 {
369 return -ENODEV;
370 }
371
omap_free_dma(int ch)372 static inline void omap_free_dma(int ch) { }
373
374 #endif /* CONFIG_ARCH_OMAP */
375
376 #endif /* __LINUX_OMAP_DMA_H */
377