1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Definitions for the NVM Express interface
4 * Copyright (c) 2011-2014, Intel Corporation.
5 */
6
7 #ifndef _LINUX_NVME_H
8 #define _LINUX_NVME_H
9
10 #include <linux/bits.h>
11 #include <linux/types.h>
12 #include <linux/uuid.h>
13
14 /* NQN names in commands fields specified one size */
15 #define NVMF_NQN_FIELD_LEN 256
16
17 /* However the max length of a qualified name is another size */
18 #define NVMF_NQN_SIZE 223
19
20 #define NVMF_TRSVCID_SIZE 32
21 #define NVMF_TRADDR_SIZE 256
22 #define NVMF_TSAS_SIZE 256
23
24 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
25
26 #define NVME_RDMA_IP_PORT 4420
27
28 #define NVME_NSID_ALL 0xffffffff
29
30 enum nvme_subsys_type {
31 NVME_NQN_DISC = 1, /* Discovery type target subsystem */
32 NVME_NQN_NVME = 2, /* NVME type target subsystem */
33 };
34
35 /* Address Family codes for Discovery Log Page entry ADRFAM field */
36 enum {
37 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
38 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
39 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
40 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
41 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
42 };
43
44 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
45 enum {
46 NVMF_TRTYPE_RDMA = 1, /* RDMA */
47 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
48 NVMF_TRTYPE_TCP = 3, /* TCP/IP */
49 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
50 NVMF_TRTYPE_MAX,
51 };
52
53 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
54 enum {
55 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
56 NVMF_TREQ_REQUIRED = 1, /* Required */
57 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
58 #define NVME_TREQ_SECURE_CHANNEL_MASK \
59 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
60
61 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */
62 };
63
64 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
65 * RDMA_QPTYPE field
66 */
67 enum {
68 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
69 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
70 };
71
72 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
73 * RDMA_QPTYPE field
74 */
75 enum {
76 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
77 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
78 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
79 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
80 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
81 };
82
83 /* RDMA Connection Management Service Type codes for Discovery Log Page
84 * entry TSAS RDMA_CMS field
85 */
86 enum {
87 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
88 };
89
90 #define NVME_AQ_DEPTH 32
91 #define NVME_NR_AEN_COMMANDS 1
92 #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
93
94 /*
95 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
96 * NVM-Express 1.2 specification, section 4.1.2.
97 */
98 #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1)
99
100 enum {
101 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
102 NVME_REG_VS = 0x0008, /* Version */
103 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
104 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
105 NVME_REG_CC = 0x0014, /* Controller Configuration */
106 NVME_REG_CSTS = 0x001c, /* Controller Status */
107 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
108 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
109 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
110 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
111 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
112 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
113 NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */
114 NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */
115 NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer
116 * Location
117 */
118 NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */
119 NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */
120 NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */
121 NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity
122 * Buffer Size
123 */
124 NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained
125 * Write Throughput
126 */
127 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
128 };
129
130 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
131 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
132 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
133 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
134 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
135 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
136
137 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
138 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
139
140 enum {
141 NVME_CMBSZ_SQS = 1 << 0,
142 NVME_CMBSZ_CQS = 1 << 1,
143 NVME_CMBSZ_LISTS = 1 << 2,
144 NVME_CMBSZ_RDS = 1 << 3,
145 NVME_CMBSZ_WDS = 1 << 4,
146
147 NVME_CMBSZ_SZ_SHIFT = 12,
148 NVME_CMBSZ_SZ_MASK = 0xfffff,
149
150 NVME_CMBSZ_SZU_SHIFT = 8,
151 NVME_CMBSZ_SZU_MASK = 0xf,
152 };
153
154 /*
155 * Submission and Completion Queue Entry Sizes for the NVM command set.
156 * (In bytes and specified as a power of two (2^n)).
157 */
158 #define NVME_ADM_SQES 6
159 #define NVME_NVM_IOSQES 6
160 #define NVME_NVM_IOCQES 4
161
162 enum {
163 NVME_CC_ENABLE = 1 << 0,
164 NVME_CC_CSS_NVM = 0 << 4,
165 NVME_CC_EN_SHIFT = 0,
166 NVME_CC_CSS_SHIFT = 4,
167 NVME_CC_MPS_SHIFT = 7,
168 NVME_CC_AMS_SHIFT = 11,
169 NVME_CC_SHN_SHIFT = 14,
170 NVME_CC_IOSQES_SHIFT = 16,
171 NVME_CC_IOCQES_SHIFT = 20,
172 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
173 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
174 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
175 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
176 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
177 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
178 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
179 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
180 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
181 NVME_CSTS_RDY = 1 << 0,
182 NVME_CSTS_CFS = 1 << 1,
183 NVME_CSTS_NSSRO = 1 << 4,
184 NVME_CSTS_PP = 1 << 5,
185 NVME_CSTS_SHST_NORMAL = 0 << 2,
186 NVME_CSTS_SHST_OCCUR = 1 << 2,
187 NVME_CSTS_SHST_CMPLT = 2 << 2,
188 NVME_CSTS_SHST_MASK = 3 << 2,
189 };
190
191 struct nvme_id_power_state {
192 __le16 max_power; /* centiwatts */
193 __u8 rsvd2;
194 __u8 flags;
195 __le32 entry_lat; /* microseconds */
196 __le32 exit_lat; /* microseconds */
197 __u8 read_tput;
198 __u8 read_lat;
199 __u8 write_tput;
200 __u8 write_lat;
201 __le16 idle_power;
202 __u8 idle_scale;
203 __u8 rsvd19;
204 __le16 active_power;
205 __u8 active_work_scale;
206 __u8 rsvd23[9];
207 };
208
209 enum {
210 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
211 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
212 };
213
214 enum nvme_ctrl_attr {
215 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0),
216 NVME_CTRL_ATTR_TBKAS = (1 << 6),
217 };
218
219 struct nvme_id_ctrl {
220 __le16 vid;
221 __le16 ssvid;
222 char sn[20];
223 char mn[40];
224 char fr[8];
225 __u8 rab;
226 __u8 ieee[3];
227 __u8 cmic;
228 __u8 mdts;
229 __le16 cntlid;
230 __le32 ver;
231 __le32 rtd3r;
232 __le32 rtd3e;
233 __le32 oaes;
234 __le32 ctratt;
235 __u8 rsvd100[28];
236 __le16 crdt1;
237 __le16 crdt2;
238 __le16 crdt3;
239 __u8 rsvd134[122];
240 __le16 oacs;
241 __u8 acl;
242 __u8 aerl;
243 __u8 frmw;
244 __u8 lpa;
245 __u8 elpe;
246 __u8 npss;
247 __u8 avscc;
248 __u8 apsta;
249 __le16 wctemp;
250 __le16 cctemp;
251 __le16 mtfa;
252 __le32 hmpre;
253 __le32 hmmin;
254 __u8 tnvmcap[16];
255 __u8 unvmcap[16];
256 __le32 rpmbs;
257 __le16 edstt;
258 __u8 dsto;
259 __u8 fwug;
260 __le16 kas;
261 __le16 hctma;
262 __le16 mntmt;
263 __le16 mxtmt;
264 __le32 sanicap;
265 __le32 hmminds;
266 __le16 hmmaxd;
267 __u8 rsvd338[4];
268 __u8 anatt;
269 __u8 anacap;
270 __le32 anagrpmax;
271 __le32 nanagrpid;
272 __u8 rsvd352[160];
273 __u8 sqes;
274 __u8 cqes;
275 __le16 maxcmd;
276 __le32 nn;
277 __le16 oncs;
278 __le16 fuses;
279 __u8 fna;
280 __u8 vwc;
281 __le16 awun;
282 __le16 awupf;
283 __u8 nvscc;
284 __u8 nwpc;
285 __le16 acwu;
286 __u8 rsvd534[2];
287 __le32 sgls;
288 __le32 mnan;
289 __u8 rsvd544[224];
290 char subnqn[256];
291 __u8 rsvd1024[768];
292 __le32 ioccsz;
293 __le32 iorcsz;
294 __le16 icdoff;
295 __u8 ctrattr;
296 __u8 msdbd;
297 __u8 rsvd1804[244];
298 struct nvme_id_power_state psd[32];
299 __u8 vs[1024];
300 };
301
302 enum {
303 NVME_CTRL_ONCS_COMPARE = 1 << 0,
304 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
305 NVME_CTRL_ONCS_DSM = 1 << 2,
306 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
307 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
308 NVME_CTRL_VWC_PRESENT = 1 << 0,
309 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
310 NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
311 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
312 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
313 NVME_CTRL_CTRATT_128_ID = 1 << 0,
314 NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1,
315 NVME_CTRL_CTRATT_NVM_SETS = 1 << 2,
316 NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3,
317 NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4,
318 NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5,
319 NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7,
320 NVME_CTRL_CTRATT_UUID_LIST = 1 << 9,
321 };
322
323 struct nvme_lbaf {
324 __le16 ms;
325 __u8 ds;
326 __u8 rp;
327 };
328
329 struct nvme_id_ns {
330 __le64 nsze;
331 __le64 ncap;
332 __le64 nuse;
333 __u8 nsfeat;
334 __u8 nlbaf;
335 __u8 flbas;
336 __u8 mc;
337 __u8 dpc;
338 __u8 dps;
339 __u8 nmic;
340 __u8 rescap;
341 __u8 fpi;
342 __u8 dlfeat;
343 __le16 nawun;
344 __le16 nawupf;
345 __le16 nacwu;
346 __le16 nabsn;
347 __le16 nabo;
348 __le16 nabspf;
349 __le16 noiob;
350 __u8 nvmcap[16];
351 __le16 npwg;
352 __le16 npwa;
353 __le16 npdg;
354 __le16 npda;
355 __le16 nows;
356 __u8 rsvd74[18];
357 __le32 anagrpid;
358 __u8 rsvd96[3];
359 __u8 nsattr;
360 __le16 nvmsetid;
361 __le16 endgid;
362 __u8 nguid[16];
363 __u8 eui64[8];
364 struct nvme_lbaf lbaf[16];
365 __u8 rsvd192[192];
366 __u8 vs[3712];
367 };
368
369 enum {
370 NVME_ID_CNS_NS = 0x00,
371 NVME_ID_CNS_CTRL = 0x01,
372 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
373 NVME_ID_CNS_NS_DESC_LIST = 0x03,
374 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
375 NVME_ID_CNS_NS_PRESENT = 0x11,
376 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
377 NVME_ID_CNS_CTRL_LIST = 0x13,
378 NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15,
379 NVME_ID_CNS_NS_GRANULARITY = 0x16,
380 NVME_ID_CNS_UUID_LIST = 0x17,
381 };
382
383 enum {
384 NVME_DIR_IDENTIFY = 0x00,
385 NVME_DIR_STREAMS = 0x01,
386 NVME_DIR_SND_ID_OP_ENABLE = 0x01,
387 NVME_DIR_SND_ST_OP_REL_ID = 0x01,
388 NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
389 NVME_DIR_RCV_ID_OP_PARAM = 0x01,
390 NVME_DIR_RCV_ST_OP_PARAM = 0x01,
391 NVME_DIR_RCV_ST_OP_STATUS = 0x02,
392 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
393 NVME_DIR_ENDIR = 0x01,
394 };
395
396 enum {
397 NVME_NS_FEAT_THIN = 1 << 0,
398 NVME_NS_FLBAS_LBA_MASK = 0xf,
399 NVME_NS_FLBAS_META_EXT = 0x10,
400 NVME_LBAF_RP_BEST = 0,
401 NVME_LBAF_RP_BETTER = 1,
402 NVME_LBAF_RP_GOOD = 2,
403 NVME_LBAF_RP_DEGRADED = 3,
404 NVME_NS_DPC_PI_LAST = 1 << 4,
405 NVME_NS_DPC_PI_FIRST = 1 << 3,
406 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
407 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
408 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
409 NVME_NS_DPS_PI_FIRST = 1 << 3,
410 NVME_NS_DPS_PI_MASK = 0x7,
411 NVME_NS_DPS_PI_TYPE1 = 1,
412 NVME_NS_DPS_PI_TYPE2 = 2,
413 NVME_NS_DPS_PI_TYPE3 = 3,
414 };
415
416 struct nvme_ns_id_desc {
417 __u8 nidt;
418 __u8 nidl;
419 __le16 reserved;
420 };
421
422 #define NVME_NIDT_EUI64_LEN 8
423 #define NVME_NIDT_NGUID_LEN 16
424 #define NVME_NIDT_UUID_LEN 16
425
426 enum {
427 NVME_NIDT_EUI64 = 0x01,
428 NVME_NIDT_NGUID = 0x02,
429 NVME_NIDT_UUID = 0x03,
430 };
431
432 struct nvme_smart_log {
433 __u8 critical_warning;
434 __u8 temperature[2];
435 __u8 avail_spare;
436 __u8 spare_thresh;
437 __u8 percent_used;
438 __u8 endu_grp_crit_warn_sumry;
439 __u8 rsvd7[25];
440 __u8 data_units_read[16];
441 __u8 data_units_written[16];
442 __u8 host_reads[16];
443 __u8 host_writes[16];
444 __u8 ctrl_busy_time[16];
445 __u8 power_cycles[16];
446 __u8 power_on_hours[16];
447 __u8 unsafe_shutdowns[16];
448 __u8 media_errors[16];
449 __u8 num_err_log_entries[16];
450 __le32 warning_temp_time;
451 __le32 critical_comp_time;
452 __le16 temp_sensor[8];
453 __le32 thm_temp1_trans_count;
454 __le32 thm_temp2_trans_count;
455 __le32 thm_temp1_total_time;
456 __le32 thm_temp2_total_time;
457 __u8 rsvd232[280];
458 };
459
460 struct nvme_fw_slot_info_log {
461 __u8 afi;
462 __u8 rsvd1[7];
463 __le64 frs[7];
464 __u8 rsvd64[448];
465 };
466
467 enum {
468 NVME_CMD_EFFECTS_CSUPP = 1 << 0,
469 NVME_CMD_EFFECTS_LBCC = 1 << 1,
470 NVME_CMD_EFFECTS_NCC = 1 << 2,
471 NVME_CMD_EFFECTS_NIC = 1 << 3,
472 NVME_CMD_EFFECTS_CCC = 1 << 4,
473 NVME_CMD_EFFECTS_CSE_MASK = GENMASK(18, 16),
474 NVME_CMD_EFFECTS_UUID_SEL = 1 << 19,
475 };
476
477 struct nvme_effects_log {
478 __le32 acs[256];
479 __le32 iocs[256];
480 __u8 resv[2048];
481 };
482
483 enum nvme_ana_state {
484 NVME_ANA_OPTIMIZED = 0x01,
485 NVME_ANA_NONOPTIMIZED = 0x02,
486 NVME_ANA_INACCESSIBLE = 0x03,
487 NVME_ANA_PERSISTENT_LOSS = 0x04,
488 NVME_ANA_CHANGE = 0x0f,
489 };
490
491 struct nvme_ana_group_desc {
492 __le32 grpid;
493 __le32 nnsids;
494 __le64 chgcnt;
495 __u8 state;
496 __u8 rsvd17[15];
497 __le32 nsids[];
498 };
499
500 /* flag for the log specific field of the ANA log */
501 #define NVME_ANA_LOG_RGO (1 << 0)
502
503 struct nvme_ana_rsp_hdr {
504 __le64 chgcnt;
505 __le16 ngrps;
506 __le16 rsvd10[3];
507 };
508
509 enum {
510 NVME_SMART_CRIT_SPARE = 1 << 0,
511 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
512 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
513 NVME_SMART_CRIT_MEDIA = 1 << 3,
514 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
515 };
516
517 enum {
518 NVME_AER_ERROR = 0,
519 NVME_AER_SMART = 1,
520 NVME_AER_NOTICE = 2,
521 NVME_AER_CSS = 6,
522 NVME_AER_VS = 7,
523 };
524
525 enum {
526 NVME_AER_ERROR_PERSIST_INT_ERR = 0x03,
527 };
528
529 enum {
530 NVME_AER_NOTICE_NS_CHANGED = 0x00,
531 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
532 NVME_AER_NOTICE_ANA = 0x03,
533 NVME_AER_NOTICE_DISC_CHANGED = 0xf0,
534 };
535
536 enum {
537 NVME_AEN_BIT_NS_ATTR = 8,
538 NVME_AEN_BIT_FW_ACT = 9,
539 NVME_AEN_BIT_ANA_CHANGE = 11,
540 NVME_AEN_BIT_DISC_CHANGE = 31,
541 };
542
543 enum {
544 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR,
545 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT,
546 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE,
547 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE,
548 };
549
550 struct nvme_lba_range_type {
551 __u8 type;
552 __u8 attributes;
553 __u8 rsvd2[14];
554 __u64 slba;
555 __u64 nlb;
556 __u8 guid[16];
557 __u8 rsvd48[16];
558 };
559
560 enum {
561 NVME_LBART_TYPE_FS = 0x01,
562 NVME_LBART_TYPE_RAID = 0x02,
563 NVME_LBART_TYPE_CACHE = 0x03,
564 NVME_LBART_TYPE_SWAP = 0x04,
565
566 NVME_LBART_ATTRIB_TEMP = 1 << 0,
567 NVME_LBART_ATTRIB_HIDE = 1 << 1,
568 };
569
570 struct nvme_reservation_status {
571 __le32 gen;
572 __u8 rtype;
573 __u8 regctl[2];
574 __u8 resv5[2];
575 __u8 ptpls;
576 __u8 resv10[13];
577 struct {
578 __le16 cntlid;
579 __u8 rcsts;
580 __u8 resv3[5];
581 __le64 hostid;
582 __le64 rkey;
583 } regctl_ds[];
584 };
585
586 enum nvme_async_event_type {
587 NVME_AER_TYPE_ERROR = 0,
588 NVME_AER_TYPE_SMART = 1,
589 NVME_AER_TYPE_NOTICE = 2,
590 };
591
592 /* I/O commands */
593
594 enum nvme_opcode {
595 nvme_cmd_flush = 0x00,
596 nvme_cmd_write = 0x01,
597 nvme_cmd_read = 0x02,
598 nvme_cmd_write_uncor = 0x04,
599 nvme_cmd_compare = 0x05,
600 nvme_cmd_write_zeroes = 0x08,
601 nvme_cmd_dsm = 0x09,
602 nvme_cmd_verify = 0x0c,
603 nvme_cmd_resv_register = 0x0d,
604 nvme_cmd_resv_report = 0x0e,
605 nvme_cmd_resv_acquire = 0x11,
606 nvme_cmd_resv_release = 0x15,
607 };
608
609 #define nvme_opcode_name(opcode) { opcode, #opcode }
610 #define show_nvm_opcode_name(val) \
611 __print_symbolic(val, \
612 nvme_opcode_name(nvme_cmd_flush), \
613 nvme_opcode_name(nvme_cmd_write), \
614 nvme_opcode_name(nvme_cmd_read), \
615 nvme_opcode_name(nvme_cmd_write_uncor), \
616 nvme_opcode_name(nvme_cmd_compare), \
617 nvme_opcode_name(nvme_cmd_write_zeroes), \
618 nvme_opcode_name(nvme_cmd_dsm), \
619 nvme_opcode_name(nvme_cmd_resv_register), \
620 nvme_opcode_name(nvme_cmd_resv_report), \
621 nvme_opcode_name(nvme_cmd_resv_acquire), \
622 nvme_opcode_name(nvme_cmd_resv_release))
623
624
625 /*
626 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
627 *
628 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
629 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
630 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
631 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
632 * request subtype
633 */
634 enum {
635 NVME_SGL_FMT_ADDRESS = 0x00,
636 NVME_SGL_FMT_OFFSET = 0x01,
637 NVME_SGL_FMT_TRANSPORT_A = 0x0A,
638 NVME_SGL_FMT_INVALIDATE = 0x0f,
639 };
640
641 /*
642 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
643 *
644 * For struct nvme_sgl_desc:
645 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
646 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
647 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
648 *
649 * For struct nvme_keyed_sgl_desc:
650 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
651 *
652 * Transport-specific SGL types:
653 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
654 */
655 enum {
656 NVME_SGL_FMT_DATA_DESC = 0x00,
657 NVME_SGL_FMT_SEG_DESC = 0x02,
658 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
659 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
660 NVME_TRANSPORT_SGL_DATA_DESC = 0x05,
661 };
662
663 struct nvme_sgl_desc {
664 __le64 addr;
665 __le32 length;
666 __u8 rsvd[3];
667 __u8 type;
668 };
669
670 struct nvme_keyed_sgl_desc {
671 __le64 addr;
672 __u8 length[3];
673 __u8 key[4];
674 __u8 type;
675 };
676
677 union nvme_data_ptr {
678 struct {
679 __le64 prp1;
680 __le64 prp2;
681 };
682 struct nvme_sgl_desc sgl;
683 struct nvme_keyed_sgl_desc ksgl;
684 };
685
686 /*
687 * Lowest two bits of our flags field (FUSE field in the spec):
688 *
689 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
690 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
691 *
692 * Highest two bits in our flags field (PSDT field in the spec):
693 *
694 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
695 * If used, MPTR contains addr of single physical buffer (byte aligned).
696 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
697 * If used, MPTR contains an address of an SGL segment containing
698 * exactly 1 SGL descriptor (qword aligned).
699 */
700 enum {
701 NVME_CMD_FUSE_FIRST = (1 << 0),
702 NVME_CMD_FUSE_SECOND = (1 << 1),
703
704 NVME_CMD_SGL_METABUF = (1 << 6),
705 NVME_CMD_SGL_METASEG = (1 << 7),
706 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
707 };
708
709 struct nvme_common_command {
710 __u8 opcode;
711 __u8 flags;
712 __u16 command_id;
713 __le32 nsid;
714 __le32 cdw2[2];
715 __le64 metadata;
716 union nvme_data_ptr dptr;
717 __le32 cdw10;
718 __le32 cdw11;
719 __le32 cdw12;
720 __le32 cdw13;
721 __le32 cdw14;
722 __le32 cdw15;
723 };
724
725 struct nvme_rw_command {
726 __u8 opcode;
727 __u8 flags;
728 __u16 command_id;
729 __le32 nsid;
730 __u64 rsvd2;
731 __le64 metadata;
732 union nvme_data_ptr dptr;
733 __le64 slba;
734 __le16 length;
735 __le16 control;
736 __le32 dsmgmt;
737 __le32 reftag;
738 __le16 apptag;
739 __le16 appmask;
740 };
741
742 enum {
743 NVME_RW_LR = 1 << 15,
744 NVME_RW_FUA = 1 << 14,
745 NVME_RW_DSM_FREQ_UNSPEC = 0,
746 NVME_RW_DSM_FREQ_TYPICAL = 1,
747 NVME_RW_DSM_FREQ_RARE = 2,
748 NVME_RW_DSM_FREQ_READS = 3,
749 NVME_RW_DSM_FREQ_WRITES = 4,
750 NVME_RW_DSM_FREQ_RW = 5,
751 NVME_RW_DSM_FREQ_ONCE = 6,
752 NVME_RW_DSM_FREQ_PREFETCH = 7,
753 NVME_RW_DSM_FREQ_TEMP = 8,
754 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
755 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
756 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
757 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
758 NVME_RW_DSM_SEQ_REQ = 1 << 6,
759 NVME_RW_DSM_COMPRESSED = 1 << 7,
760 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
761 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
762 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
763 NVME_RW_PRINFO_PRACT = 1 << 13,
764 NVME_RW_DTYPE_STREAMS = 1 << 4,
765 };
766
767 struct nvme_dsm_cmd {
768 __u8 opcode;
769 __u8 flags;
770 __u16 command_id;
771 __le32 nsid;
772 __u64 rsvd2[2];
773 union nvme_data_ptr dptr;
774 __le32 nr;
775 __le32 attributes;
776 __u32 rsvd12[4];
777 };
778
779 enum {
780 NVME_DSMGMT_IDR = 1 << 0,
781 NVME_DSMGMT_IDW = 1 << 1,
782 NVME_DSMGMT_AD = 1 << 2,
783 };
784
785 #define NVME_DSM_MAX_RANGES 256
786
787 struct nvme_dsm_range {
788 __le32 cattr;
789 __le32 nlb;
790 __le64 slba;
791 };
792
793 struct nvme_write_zeroes_cmd {
794 __u8 opcode;
795 __u8 flags;
796 __u16 command_id;
797 __le32 nsid;
798 __u64 rsvd2;
799 __le64 metadata;
800 union nvme_data_ptr dptr;
801 __le64 slba;
802 __le16 length;
803 __le16 control;
804 __le32 dsmgmt;
805 __le32 reftag;
806 __le16 apptag;
807 __le16 appmask;
808 };
809
810 /* Features */
811
812 struct nvme_feat_auto_pst {
813 __le64 entries[32];
814 };
815
816 enum {
817 NVME_HOST_MEM_ENABLE = (1 << 0),
818 NVME_HOST_MEM_RETURN = (1 << 1),
819 };
820
821 struct nvme_feat_host_behavior {
822 __u8 acre;
823 __u8 resv1[511];
824 };
825
826 enum {
827 NVME_ENABLE_ACRE = 1,
828 };
829
830 /* Admin commands */
831
832 enum nvme_admin_opcode {
833 nvme_admin_delete_sq = 0x00,
834 nvme_admin_create_sq = 0x01,
835 nvme_admin_get_log_page = 0x02,
836 nvme_admin_delete_cq = 0x04,
837 nvme_admin_create_cq = 0x05,
838 nvme_admin_identify = 0x06,
839 nvme_admin_abort_cmd = 0x08,
840 nvme_admin_set_features = 0x09,
841 nvme_admin_get_features = 0x0a,
842 nvme_admin_async_event = 0x0c,
843 nvme_admin_ns_mgmt = 0x0d,
844 nvme_admin_activate_fw = 0x10,
845 nvme_admin_download_fw = 0x11,
846 nvme_admin_dev_self_test = 0x14,
847 nvme_admin_ns_attach = 0x15,
848 nvme_admin_keep_alive = 0x18,
849 nvme_admin_directive_send = 0x19,
850 nvme_admin_directive_recv = 0x1a,
851 nvme_admin_virtual_mgmt = 0x1c,
852 nvme_admin_nvme_mi_send = 0x1d,
853 nvme_admin_nvme_mi_recv = 0x1e,
854 nvme_admin_dbbuf = 0x7C,
855 nvme_admin_format_nvm = 0x80,
856 nvme_admin_security_send = 0x81,
857 nvme_admin_security_recv = 0x82,
858 nvme_admin_sanitize_nvm = 0x84,
859 nvme_admin_get_lba_status = 0x86,
860 };
861
862 #define nvme_admin_opcode_name(opcode) { opcode, #opcode }
863 #define show_admin_opcode_name(val) \
864 __print_symbolic(val, \
865 nvme_admin_opcode_name(nvme_admin_delete_sq), \
866 nvme_admin_opcode_name(nvme_admin_create_sq), \
867 nvme_admin_opcode_name(nvme_admin_get_log_page), \
868 nvme_admin_opcode_name(nvme_admin_delete_cq), \
869 nvme_admin_opcode_name(nvme_admin_create_cq), \
870 nvme_admin_opcode_name(nvme_admin_identify), \
871 nvme_admin_opcode_name(nvme_admin_abort_cmd), \
872 nvme_admin_opcode_name(nvme_admin_set_features), \
873 nvme_admin_opcode_name(nvme_admin_get_features), \
874 nvme_admin_opcode_name(nvme_admin_async_event), \
875 nvme_admin_opcode_name(nvme_admin_ns_mgmt), \
876 nvme_admin_opcode_name(nvme_admin_activate_fw), \
877 nvme_admin_opcode_name(nvme_admin_download_fw), \
878 nvme_admin_opcode_name(nvme_admin_ns_attach), \
879 nvme_admin_opcode_name(nvme_admin_keep_alive), \
880 nvme_admin_opcode_name(nvme_admin_directive_send), \
881 nvme_admin_opcode_name(nvme_admin_directive_recv), \
882 nvme_admin_opcode_name(nvme_admin_dbbuf), \
883 nvme_admin_opcode_name(nvme_admin_format_nvm), \
884 nvme_admin_opcode_name(nvme_admin_security_send), \
885 nvme_admin_opcode_name(nvme_admin_security_recv), \
886 nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \
887 nvme_admin_opcode_name(nvme_admin_get_lba_status))
888
889 enum {
890 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
891 NVME_CQ_IRQ_ENABLED = (1 << 1),
892 NVME_SQ_PRIO_URGENT = (0 << 1),
893 NVME_SQ_PRIO_HIGH = (1 << 1),
894 NVME_SQ_PRIO_MEDIUM = (2 << 1),
895 NVME_SQ_PRIO_LOW = (3 << 1),
896 NVME_FEAT_ARBITRATION = 0x01,
897 NVME_FEAT_POWER_MGMT = 0x02,
898 NVME_FEAT_LBA_RANGE = 0x03,
899 NVME_FEAT_TEMP_THRESH = 0x04,
900 NVME_FEAT_ERR_RECOVERY = 0x05,
901 NVME_FEAT_VOLATILE_WC = 0x06,
902 NVME_FEAT_NUM_QUEUES = 0x07,
903 NVME_FEAT_IRQ_COALESCE = 0x08,
904 NVME_FEAT_IRQ_CONFIG = 0x09,
905 NVME_FEAT_WRITE_ATOMIC = 0x0a,
906 NVME_FEAT_ASYNC_EVENT = 0x0b,
907 NVME_FEAT_AUTO_PST = 0x0c,
908 NVME_FEAT_HOST_MEM_BUF = 0x0d,
909 NVME_FEAT_TIMESTAMP = 0x0e,
910 NVME_FEAT_KATO = 0x0f,
911 NVME_FEAT_HCTM = 0x10,
912 NVME_FEAT_NOPSC = 0x11,
913 NVME_FEAT_RRL = 0x12,
914 NVME_FEAT_PLM_CONFIG = 0x13,
915 NVME_FEAT_PLM_WINDOW = 0x14,
916 NVME_FEAT_HOST_BEHAVIOR = 0x16,
917 NVME_FEAT_SANITIZE = 0x17,
918 NVME_FEAT_SW_PROGRESS = 0x80,
919 NVME_FEAT_HOST_ID = 0x81,
920 NVME_FEAT_RESV_MASK = 0x82,
921 NVME_FEAT_RESV_PERSIST = 0x83,
922 NVME_FEAT_WRITE_PROTECT = 0x84,
923 NVME_LOG_ERROR = 0x01,
924 NVME_LOG_SMART = 0x02,
925 NVME_LOG_FW_SLOT = 0x03,
926 NVME_LOG_CHANGED_NS = 0x04,
927 NVME_LOG_CMD_EFFECTS = 0x05,
928 NVME_LOG_DEVICE_SELF_TEST = 0x06,
929 NVME_LOG_TELEMETRY_HOST = 0x07,
930 NVME_LOG_TELEMETRY_CTRL = 0x08,
931 NVME_LOG_ENDURANCE_GROUP = 0x09,
932 NVME_LOG_ANA = 0x0c,
933 NVME_LOG_DISC = 0x70,
934 NVME_LOG_RESERVATION = 0x80,
935 NVME_FWACT_REPL = (0 << 3),
936 NVME_FWACT_REPL_ACTV = (1 << 3),
937 NVME_FWACT_ACTV = (2 << 3),
938 };
939
940 /* NVMe Namespace Write Protect State */
941 enum {
942 NVME_NS_NO_WRITE_PROTECT = 0,
943 NVME_NS_WRITE_PROTECT,
944 NVME_NS_WRITE_PROTECT_POWER_CYCLE,
945 NVME_NS_WRITE_PROTECT_PERMANENT,
946 };
947
948 #define NVME_MAX_CHANGED_NAMESPACES 1024
949
950 struct nvme_identify {
951 __u8 opcode;
952 __u8 flags;
953 __u16 command_id;
954 __le32 nsid;
955 __u64 rsvd2[2];
956 union nvme_data_ptr dptr;
957 __u8 cns;
958 __u8 rsvd3;
959 __le16 ctrlid;
960 __u32 rsvd11[5];
961 };
962
963 #define NVME_IDENTIFY_DATA_SIZE 4096
964
965 struct nvme_features {
966 __u8 opcode;
967 __u8 flags;
968 __u16 command_id;
969 __le32 nsid;
970 __u64 rsvd2[2];
971 union nvme_data_ptr dptr;
972 __le32 fid;
973 __le32 dword11;
974 __le32 dword12;
975 __le32 dword13;
976 __le32 dword14;
977 __le32 dword15;
978 };
979
980 struct nvme_host_mem_buf_desc {
981 __le64 addr;
982 __le32 size;
983 __u32 rsvd;
984 };
985
986 struct nvme_create_cq {
987 __u8 opcode;
988 __u8 flags;
989 __u16 command_id;
990 __u32 rsvd1[5];
991 __le64 prp1;
992 __u64 rsvd8;
993 __le16 cqid;
994 __le16 qsize;
995 __le16 cq_flags;
996 __le16 irq_vector;
997 __u32 rsvd12[4];
998 };
999
1000 struct nvme_create_sq {
1001 __u8 opcode;
1002 __u8 flags;
1003 __u16 command_id;
1004 __u32 rsvd1[5];
1005 __le64 prp1;
1006 __u64 rsvd8;
1007 __le16 sqid;
1008 __le16 qsize;
1009 __le16 sq_flags;
1010 __le16 cqid;
1011 __u32 rsvd12[4];
1012 };
1013
1014 struct nvme_delete_queue {
1015 __u8 opcode;
1016 __u8 flags;
1017 __u16 command_id;
1018 __u32 rsvd1[9];
1019 __le16 qid;
1020 __u16 rsvd10;
1021 __u32 rsvd11[5];
1022 };
1023
1024 struct nvme_abort_cmd {
1025 __u8 opcode;
1026 __u8 flags;
1027 __u16 command_id;
1028 __u32 rsvd1[9];
1029 __le16 sqid;
1030 __u16 cid;
1031 __u32 rsvd11[5];
1032 };
1033
1034 struct nvme_download_firmware {
1035 __u8 opcode;
1036 __u8 flags;
1037 __u16 command_id;
1038 __u32 rsvd1[5];
1039 union nvme_data_ptr dptr;
1040 __le32 numd;
1041 __le32 offset;
1042 __u32 rsvd12[4];
1043 };
1044
1045 struct nvme_format_cmd {
1046 __u8 opcode;
1047 __u8 flags;
1048 __u16 command_id;
1049 __le32 nsid;
1050 __u64 rsvd2[4];
1051 __le32 cdw10;
1052 __u32 rsvd11[5];
1053 };
1054
1055 struct nvme_get_log_page_command {
1056 __u8 opcode;
1057 __u8 flags;
1058 __u16 command_id;
1059 __le32 nsid;
1060 __u64 rsvd2[2];
1061 union nvme_data_ptr dptr;
1062 __u8 lid;
1063 __u8 lsp; /* upper 4 bits reserved */
1064 __le16 numdl;
1065 __le16 numdu;
1066 __u16 rsvd11;
1067 union {
1068 struct {
1069 __le32 lpol;
1070 __le32 lpou;
1071 };
1072 __le64 lpo;
1073 };
1074 __u32 rsvd14[2];
1075 };
1076
1077 struct nvme_directive_cmd {
1078 __u8 opcode;
1079 __u8 flags;
1080 __u16 command_id;
1081 __le32 nsid;
1082 __u64 rsvd2[2];
1083 union nvme_data_ptr dptr;
1084 __le32 numd;
1085 __u8 doper;
1086 __u8 dtype;
1087 __le16 dspec;
1088 __u8 endir;
1089 __u8 tdtype;
1090 __u16 rsvd15;
1091
1092 __u32 rsvd16[3];
1093 };
1094
1095 /*
1096 * Fabrics subcommands.
1097 */
1098 enum nvmf_fabrics_opcode {
1099 nvme_fabrics_command = 0x7f,
1100 };
1101
1102 enum nvmf_capsule_command {
1103 nvme_fabrics_type_property_set = 0x00,
1104 nvme_fabrics_type_connect = 0x01,
1105 nvme_fabrics_type_property_get = 0x04,
1106 };
1107
1108 #define nvme_fabrics_type_name(type) { type, #type }
1109 #define show_fabrics_type_name(type) \
1110 __print_symbolic(type, \
1111 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
1112 nvme_fabrics_type_name(nvme_fabrics_type_connect), \
1113 nvme_fabrics_type_name(nvme_fabrics_type_property_get))
1114
1115 /*
1116 * If not fabrics command, fctype will be ignored.
1117 */
1118 #define show_opcode_name(qid, opcode, fctype) \
1119 ((opcode) == nvme_fabrics_command ? \
1120 show_fabrics_type_name(fctype) : \
1121 ((qid) ? \
1122 show_nvm_opcode_name(opcode) : \
1123 show_admin_opcode_name(opcode)))
1124
1125 struct nvmf_common_command {
1126 __u8 opcode;
1127 __u8 resv1;
1128 __u16 command_id;
1129 __u8 fctype;
1130 __u8 resv2[35];
1131 __u8 ts[24];
1132 };
1133
1134 /*
1135 * The legal cntlid range a NVMe Target will provide.
1136 * Note that cntlid of value 0 is considered illegal in the fabrics world.
1137 * Devices based on earlier specs did not have the subsystem concept;
1138 * therefore, those devices had their cntlid value set to 0 as a result.
1139 */
1140 #define NVME_CNTLID_MIN 1
1141 #define NVME_CNTLID_MAX 0xffef
1142 #define NVME_CNTLID_DYNAMIC 0xffff
1143
1144 #define MAX_DISC_LOGS 255
1145
1146 /* Discovery log page entry */
1147 struct nvmf_disc_rsp_page_entry {
1148 __u8 trtype;
1149 __u8 adrfam;
1150 __u8 subtype;
1151 __u8 treq;
1152 __le16 portid;
1153 __le16 cntlid;
1154 __le16 asqsz;
1155 __u8 resv8[22];
1156 char trsvcid[NVMF_TRSVCID_SIZE];
1157 __u8 resv64[192];
1158 char subnqn[NVMF_NQN_FIELD_LEN];
1159 char traddr[NVMF_TRADDR_SIZE];
1160 union tsas {
1161 char common[NVMF_TSAS_SIZE];
1162 struct rdma {
1163 __u8 qptype;
1164 __u8 prtype;
1165 __u8 cms;
1166 __u8 resv3[5];
1167 __u16 pkey;
1168 __u8 resv10[246];
1169 } rdma;
1170 } tsas;
1171 };
1172
1173 /* Discovery log page header */
1174 struct nvmf_disc_rsp_page_hdr {
1175 __le64 genctr;
1176 __le64 numrec;
1177 __le16 recfmt;
1178 __u8 resv14[1006];
1179 struct nvmf_disc_rsp_page_entry entries[0];
1180 };
1181
1182 enum {
1183 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2),
1184 };
1185
1186 struct nvmf_connect_command {
1187 __u8 opcode;
1188 __u8 resv1;
1189 __u16 command_id;
1190 __u8 fctype;
1191 __u8 resv2[19];
1192 union nvme_data_ptr dptr;
1193 __le16 recfmt;
1194 __le16 qid;
1195 __le16 sqsize;
1196 __u8 cattr;
1197 __u8 resv3;
1198 __le32 kato;
1199 __u8 resv4[12];
1200 };
1201
1202 struct nvmf_connect_data {
1203 uuid_t hostid;
1204 __le16 cntlid;
1205 char resv4[238];
1206 char subsysnqn[NVMF_NQN_FIELD_LEN];
1207 char hostnqn[NVMF_NQN_FIELD_LEN];
1208 char resv5[256];
1209 };
1210
1211 struct nvmf_property_set_command {
1212 __u8 opcode;
1213 __u8 resv1;
1214 __u16 command_id;
1215 __u8 fctype;
1216 __u8 resv2[35];
1217 __u8 attrib;
1218 __u8 resv3[3];
1219 __le32 offset;
1220 __le64 value;
1221 __u8 resv4[8];
1222 };
1223
1224 struct nvmf_property_get_command {
1225 __u8 opcode;
1226 __u8 resv1;
1227 __u16 command_id;
1228 __u8 fctype;
1229 __u8 resv2[35];
1230 __u8 attrib;
1231 __u8 resv3[3];
1232 __le32 offset;
1233 __u8 resv4[16];
1234 };
1235
1236 struct nvme_dbbuf {
1237 __u8 opcode;
1238 __u8 flags;
1239 __u16 command_id;
1240 __u32 rsvd1[5];
1241 __le64 prp1;
1242 __le64 prp2;
1243 __u32 rsvd12[6];
1244 };
1245
1246 struct streams_directive_params {
1247 __le16 msl;
1248 __le16 nssa;
1249 __le16 nsso;
1250 __u8 rsvd[10];
1251 __le32 sws;
1252 __le16 sgs;
1253 __le16 nsa;
1254 __le16 nso;
1255 __u8 rsvd2[6];
1256 };
1257
1258 struct nvme_command {
1259 union {
1260 struct nvme_common_command common;
1261 struct nvme_rw_command rw;
1262 struct nvme_identify identify;
1263 struct nvme_features features;
1264 struct nvme_create_cq create_cq;
1265 struct nvme_create_sq create_sq;
1266 struct nvme_delete_queue delete_queue;
1267 struct nvme_download_firmware dlfw;
1268 struct nvme_format_cmd format;
1269 struct nvme_dsm_cmd dsm;
1270 struct nvme_write_zeroes_cmd write_zeroes;
1271 struct nvme_abort_cmd abort;
1272 struct nvme_get_log_page_command get_log_page;
1273 struct nvmf_common_command fabrics;
1274 struct nvmf_connect_command connect;
1275 struct nvmf_property_set_command prop_set;
1276 struct nvmf_property_get_command prop_get;
1277 struct nvme_dbbuf dbbuf;
1278 struct nvme_directive_cmd directive;
1279 };
1280 };
1281
nvme_is_fabrics(struct nvme_command * cmd)1282 static inline bool nvme_is_fabrics(struct nvme_command *cmd)
1283 {
1284 return cmd->common.opcode == nvme_fabrics_command;
1285 }
1286
1287 struct nvme_error_slot {
1288 __le64 error_count;
1289 __le16 sqid;
1290 __le16 cmdid;
1291 __le16 status_field;
1292 __le16 param_error_location;
1293 __le64 lba;
1294 __le32 nsid;
1295 __u8 vs;
1296 __u8 resv[3];
1297 __le64 cs;
1298 __u8 resv2[24];
1299 };
1300
nvme_is_write(struct nvme_command * cmd)1301 static inline bool nvme_is_write(struct nvme_command *cmd)
1302 {
1303 /*
1304 * What a mess...
1305 *
1306 * Why can't we simply have a Fabrics In and Fabrics out command?
1307 */
1308 if (unlikely(nvme_is_fabrics(cmd)))
1309 return cmd->fabrics.fctype & 1;
1310 return cmd->common.opcode & 1;
1311 }
1312
1313 enum {
1314 /*
1315 * Generic Command Status:
1316 */
1317 NVME_SC_SUCCESS = 0x0,
1318 NVME_SC_INVALID_OPCODE = 0x1,
1319 NVME_SC_INVALID_FIELD = 0x2,
1320 NVME_SC_CMDID_CONFLICT = 0x3,
1321 NVME_SC_DATA_XFER_ERROR = 0x4,
1322 NVME_SC_POWER_LOSS = 0x5,
1323 NVME_SC_INTERNAL = 0x6,
1324 NVME_SC_ABORT_REQ = 0x7,
1325 NVME_SC_ABORT_QUEUE = 0x8,
1326 NVME_SC_FUSED_FAIL = 0x9,
1327 NVME_SC_FUSED_MISSING = 0xa,
1328 NVME_SC_INVALID_NS = 0xb,
1329 NVME_SC_CMD_SEQ_ERROR = 0xc,
1330 NVME_SC_SGL_INVALID_LAST = 0xd,
1331 NVME_SC_SGL_INVALID_COUNT = 0xe,
1332 NVME_SC_SGL_INVALID_DATA = 0xf,
1333 NVME_SC_SGL_INVALID_METADATA = 0x10,
1334 NVME_SC_SGL_INVALID_TYPE = 0x11,
1335
1336 NVME_SC_SGL_INVALID_OFFSET = 0x16,
1337 NVME_SC_SGL_INVALID_SUBTYPE = 0x17,
1338
1339 NVME_SC_SANITIZE_FAILED = 0x1C,
1340 NVME_SC_SANITIZE_IN_PROGRESS = 0x1D,
1341
1342 NVME_SC_NS_WRITE_PROTECTED = 0x20,
1343 NVME_SC_CMD_INTERRUPTED = 0x21,
1344
1345 NVME_SC_LBA_RANGE = 0x80,
1346 NVME_SC_CAP_EXCEEDED = 0x81,
1347 NVME_SC_NS_NOT_READY = 0x82,
1348 NVME_SC_RESERVATION_CONFLICT = 0x83,
1349
1350 /*
1351 * Command Specific Status:
1352 */
1353 NVME_SC_CQ_INVALID = 0x100,
1354 NVME_SC_QID_INVALID = 0x101,
1355 NVME_SC_QUEUE_SIZE = 0x102,
1356 NVME_SC_ABORT_LIMIT = 0x103,
1357 NVME_SC_ABORT_MISSING = 0x104,
1358 NVME_SC_ASYNC_LIMIT = 0x105,
1359 NVME_SC_FIRMWARE_SLOT = 0x106,
1360 NVME_SC_FIRMWARE_IMAGE = 0x107,
1361 NVME_SC_INVALID_VECTOR = 0x108,
1362 NVME_SC_INVALID_LOG_PAGE = 0x109,
1363 NVME_SC_INVALID_FORMAT = 0x10a,
1364 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
1365 NVME_SC_INVALID_QUEUE = 0x10c,
1366 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
1367 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
1368 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
1369 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1370 NVME_SC_FW_NEEDS_RESET = 0x111,
1371 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
1372 NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113,
1373 NVME_SC_OVERLAPPING_RANGE = 0x114,
1374 NVME_SC_NS_INSUFFICIENT_CAP = 0x115,
1375 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1376 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1377 NVME_SC_NS_IS_PRIVATE = 0x119,
1378 NVME_SC_NS_NOT_ATTACHED = 0x11a,
1379 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1380 NVME_SC_CTRL_LIST_INVALID = 0x11c,
1381 NVME_SC_BP_WRITE_PROHIBITED = 0x11e,
1382 NVME_SC_PMR_SAN_PROHIBITED = 0x123,
1383
1384 /*
1385 * I/O Command Set Specific - NVM commands:
1386 */
1387 NVME_SC_BAD_ATTRIBUTES = 0x180,
1388 NVME_SC_INVALID_PI = 0x181,
1389 NVME_SC_READ_ONLY = 0x182,
1390 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
1391
1392 /*
1393 * I/O Command Set Specific - Fabrics commands:
1394 */
1395 NVME_SC_CONNECT_FORMAT = 0x180,
1396 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1397 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1398 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1399 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1400
1401 NVME_SC_DISCOVERY_RESTART = 0x190,
1402 NVME_SC_AUTH_REQUIRED = 0x191,
1403
1404 /*
1405 * Media and Data Integrity Errors:
1406 */
1407 NVME_SC_WRITE_FAULT = 0x280,
1408 NVME_SC_READ_ERROR = 0x281,
1409 NVME_SC_GUARD_CHECK = 0x282,
1410 NVME_SC_APPTAG_CHECK = 0x283,
1411 NVME_SC_REFTAG_CHECK = 0x284,
1412 NVME_SC_COMPARE_FAILED = 0x285,
1413 NVME_SC_ACCESS_DENIED = 0x286,
1414 NVME_SC_UNWRITTEN_BLOCK = 0x287,
1415
1416 /*
1417 * Path-related Errors:
1418 */
1419 NVME_SC_ANA_PERSISTENT_LOSS = 0x301,
1420 NVME_SC_ANA_INACCESSIBLE = 0x302,
1421 NVME_SC_ANA_TRANSITION = 0x303,
1422 NVME_SC_HOST_PATH_ERROR = 0x370,
1423 NVME_SC_HOST_ABORTED_CMD = 0x371,
1424
1425 NVME_SC_CRD = 0x1800,
1426 NVME_SC_DNR = 0x4000,
1427 };
1428
1429 struct nvme_completion {
1430 /*
1431 * Used by Admin and Fabrics commands to return data:
1432 */
1433 union nvme_result {
1434 __le16 u16;
1435 __le32 u32;
1436 __le64 u64;
1437 } result;
1438 __le16 sq_head; /* how much of this queue may be reclaimed */
1439 __le16 sq_id; /* submission queue that generated this entry */
1440 __u16 command_id; /* of the command which completed */
1441 __le16 status; /* did the command fail, and if so, why? */
1442 };
1443
1444 #define NVME_VS(major, minor, tertiary) \
1445 (((major) << 16) | ((minor) << 8) | (tertiary))
1446
1447 #define NVME_MAJOR(ver) ((ver) >> 16)
1448 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
1449 #define NVME_TERTIARY(ver) ((ver) & 0xff)
1450
1451 #endif /* _LINUX_NVME_H */
1452