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1  /* SPDX-License-Identifier: GPL-2.0-or-later */
2  #ifndef __SOUND_CS46XX_H
3  #define __SOUND_CS46XX_H
4  
5  /*
6   *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
7   *		     Cirrus Logic, Inc.
8   *  Definitions for Cirrus Logic CS46xx chips
9   */
10  
11  #include <sound/pcm.h>
12  #include <sound/pcm-indirect.h>
13  #include <sound/rawmidi.h>
14  #include <sound/ac97_codec.h>
15  #include "cs46xx_dsp_spos.h"
16  
17  /*
18   *  Direct registers
19   */
20  
21  /*
22   *  The following define the offsets of the registers accessed via base address
23   *  register zero on the CS46xx part.
24   */
25  #define BA0_HISR				0x00000000
26  #define BA0_HSR0                                0x00000004
27  #define BA0_HICR                                0x00000008
28  #define BA0_DMSR                                0x00000100
29  #define BA0_HSAR                                0x00000110
30  #define BA0_HDAR                                0x00000114
31  #define BA0_HDMR                                0x00000118
32  #define BA0_HDCR                                0x0000011C
33  #define BA0_PFMC                                0x00000200
34  #define BA0_PFCV1                               0x00000204
35  #define BA0_PFCV2                               0x00000208
36  #define BA0_PCICFG00                            0x00000300
37  #define BA0_PCICFG04                            0x00000304
38  #define BA0_PCICFG08                            0x00000308
39  #define BA0_PCICFG0C                            0x0000030C
40  #define BA0_PCICFG10                            0x00000310
41  #define BA0_PCICFG14                            0x00000314
42  #define BA0_PCICFG18                            0x00000318
43  #define BA0_PCICFG1C                            0x0000031C
44  #define BA0_PCICFG20                            0x00000320
45  #define BA0_PCICFG24                            0x00000324
46  #define BA0_PCICFG28                            0x00000328
47  #define BA0_PCICFG2C                            0x0000032C
48  #define BA0_PCICFG30                            0x00000330
49  #define BA0_PCICFG34                            0x00000334
50  #define BA0_PCICFG38                            0x00000338
51  #define BA0_PCICFG3C                            0x0000033C
52  #define BA0_CLKCR1                              0x00000400
53  #define BA0_CLKCR2                              0x00000404
54  #define BA0_PLLM                                0x00000408
55  #define BA0_PLLCC                               0x0000040C
56  #define BA0_FRR                                 0x00000410
57  #define BA0_CFL1                                0x00000414
58  #define BA0_CFL2                                0x00000418
59  #define BA0_SERMC1                              0x00000420
60  #define BA0_SERMC2                              0x00000424
61  #define BA0_SERC1                               0x00000428
62  #define BA0_SERC2                               0x0000042C
63  #define BA0_SERC3                               0x00000430
64  #define BA0_SERC4                               0x00000434
65  #define BA0_SERC5                               0x00000438
66  #define BA0_SERBSP                              0x0000043C
67  #define BA0_SERBST                              0x00000440
68  #define BA0_SERBCM                              0x00000444
69  #define BA0_SERBAD                              0x00000448
70  #define BA0_SERBCF                              0x0000044C
71  #define BA0_SERBWP                              0x00000450
72  #define BA0_SERBRP                              0x00000454
73  #ifndef NO_CS4612
74  #define BA0_ASER_FADDR                          0x00000458
75  #endif
76  #define BA0_ACCTL                               0x00000460
77  #define BA0_ACSTS                               0x00000464
78  #define BA0_ACOSV                               0x00000468
79  #define BA0_ACCAD                               0x0000046C
80  #define BA0_ACCDA                               0x00000470
81  #define BA0_ACISV                               0x00000474
82  #define BA0_ACSAD                               0x00000478
83  #define BA0_ACSDA                               0x0000047C
84  #define BA0_JSPT                                0x00000480
85  #define BA0_JSCTL                               0x00000484
86  #define BA0_JSC1                                0x00000488
87  #define BA0_JSC2                                0x0000048C
88  #define BA0_MIDCR                               0x00000490
89  #define BA0_MIDSR                               0x00000494
90  #define BA0_MIDWP                               0x00000498
91  #define BA0_MIDRP                               0x0000049C
92  #define BA0_JSIO                                0x000004A0
93  #ifndef NO_CS4612
94  #define BA0_ASER_MASTER                         0x000004A4
95  #endif
96  #define BA0_CFGI                                0x000004B0
97  #define BA0_SSVID                               0x000004B4
98  #define BA0_GPIOR                               0x000004B8
99  #ifndef NO_CS4612
100  #define BA0_EGPIODR                             0x000004BC
101  #define BA0_EGPIOPTR                            0x000004C0
102  #define BA0_EGPIOTR                             0x000004C4
103  #define BA0_EGPIOWR                             0x000004C8
104  #define BA0_EGPIOSR                             0x000004CC
105  #define BA0_SERC6                               0x000004D0
106  #define BA0_SERC7                               0x000004D4
107  #define BA0_SERACC                              0x000004D8
108  #define BA0_ACCTL2                              0x000004E0
109  #define BA0_ACSTS2                              0x000004E4
110  #define BA0_ACOSV2                              0x000004E8
111  #define BA0_ACCAD2                              0x000004EC
112  #define BA0_ACCDA2                              0x000004F0
113  #define BA0_ACISV2                              0x000004F4
114  #define BA0_ACSAD2                              0x000004F8
115  #define BA0_ACSDA2                              0x000004FC
116  #define BA0_IOTAC0                              0x00000500
117  #define BA0_IOTAC1                              0x00000504
118  #define BA0_IOTAC2                              0x00000508
119  #define BA0_IOTAC3                              0x0000050C
120  #define BA0_IOTAC4                              0x00000510
121  #define BA0_IOTAC5                              0x00000514
122  #define BA0_IOTAC6                              0x00000518
123  #define BA0_IOTAC7                              0x0000051C
124  #define BA0_IOTAC8                              0x00000520
125  #define BA0_IOTAC9                              0x00000524
126  #define BA0_IOTAC10                             0x00000528
127  #define BA0_IOTAC11                             0x0000052C
128  #define BA0_IOTFR0                              0x00000540
129  #define BA0_IOTFR1                              0x00000544
130  #define BA0_IOTFR2                              0x00000548
131  #define BA0_IOTFR3                              0x0000054C
132  #define BA0_IOTFR4                              0x00000550
133  #define BA0_IOTFR5                              0x00000554
134  #define BA0_IOTFR6                              0x00000558
135  #define BA0_IOTFR7                              0x0000055C
136  #define BA0_IOTFIFO                             0x00000580
137  #define BA0_IOTRRD                              0x00000584
138  #define BA0_IOTFP                               0x00000588
139  #define BA0_IOTCR                               0x0000058C
140  #define BA0_DPCID                               0x00000590
141  #define BA0_DPCIA                               0x00000594
142  #define BA0_DPCIC                               0x00000598
143  #define BA0_PCPCIR                              0x00000600
144  #define BA0_PCPCIG                              0x00000604
145  #define BA0_PCPCIEN                             0x00000608
146  #define BA0_EPCIPMC                             0x00000610
147  #endif
148  
149  /*
150   *  The following define the offsets of the registers and memories accessed via
151   *  base address register one on the CS46xx part.
152   */
153  #define BA1_SP_DMEM0                            0x00000000
154  #define BA1_SP_DMEM1                            0x00010000
155  #define BA1_SP_PMEM                             0x00020000
156  #define BA1_SP_REG				0x00030000
157  #define BA1_SPCR                                0x00030000
158  #define BA1_DREG                                0x00030004
159  #define BA1_DSRWP                               0x00030008
160  #define BA1_TWPR                                0x0003000C
161  #define BA1_SPWR                                0x00030010
162  #define BA1_SPIR                                0x00030014
163  #define BA1_FGR1                                0x00030020
164  #define BA1_SPCS                                0x00030028
165  #define BA1_SDSR                                0x0003002C
166  #define BA1_FRMT                                0x00030030
167  #define BA1_FRCC                                0x00030034
168  #define BA1_FRSC                                0x00030038
169  #define BA1_OMNI_MEM                            0x000E0000
170  
171  
172  /*
173   *  The following defines are for the flags in the host interrupt status
174   *  register.
175   */
176  #define HISR_VC_MASK                            0x0000FFFF
177  #define HISR_VC0                                0x00000001
178  #define HISR_VC1                                0x00000002
179  #define HISR_VC2                                0x00000004
180  #define HISR_VC3                                0x00000008
181  #define HISR_VC4                                0x00000010
182  #define HISR_VC5                                0x00000020
183  #define HISR_VC6                                0x00000040
184  #define HISR_VC7                                0x00000080
185  #define HISR_VC8                                0x00000100
186  #define HISR_VC9                                0x00000200
187  #define HISR_VC10                               0x00000400
188  #define HISR_VC11                               0x00000800
189  #define HISR_VC12                               0x00001000
190  #define HISR_VC13                               0x00002000
191  #define HISR_VC14                               0x00004000
192  #define HISR_VC15                               0x00008000
193  #define HISR_INT0                               0x00010000
194  #define HISR_INT1                               0x00020000
195  #define HISR_DMAI                               0x00040000
196  #define HISR_FROVR                              0x00080000
197  #define HISR_MIDI                               0x00100000
198  #ifdef NO_CS4612
199  #define HISR_RESERVED                           0x0FE00000
200  #else
201  #define HISR_SBINT                              0x00200000
202  #define HISR_RESERVED                           0x0FC00000
203  #endif
204  #define HISR_H0P                                0x40000000
205  #define HISR_INTENA                             0x80000000
206  
207  /*
208   *  The following defines are for the flags in the host signal register 0.
209   */
210  #define HSR0_VC_MASK                            0xFFFFFFFF
211  #define HSR0_VC16                               0x00000001
212  #define HSR0_VC17                               0x00000002
213  #define HSR0_VC18                               0x00000004
214  #define HSR0_VC19                               0x00000008
215  #define HSR0_VC20                               0x00000010
216  #define HSR0_VC21                               0x00000020
217  #define HSR0_VC22                               0x00000040
218  #define HSR0_VC23                               0x00000080
219  #define HSR0_VC24                               0x00000100
220  #define HSR0_VC25                               0x00000200
221  #define HSR0_VC26                               0x00000400
222  #define HSR0_VC27                               0x00000800
223  #define HSR0_VC28                               0x00001000
224  #define HSR0_VC29                               0x00002000
225  #define HSR0_VC30                               0x00004000
226  #define HSR0_VC31                               0x00008000
227  #define HSR0_VC32                               0x00010000
228  #define HSR0_VC33                               0x00020000
229  #define HSR0_VC34                               0x00040000
230  #define HSR0_VC35                               0x00080000
231  #define HSR0_VC36                               0x00100000
232  #define HSR0_VC37                               0x00200000
233  #define HSR0_VC38                               0x00400000
234  #define HSR0_VC39                               0x00800000
235  #define HSR0_VC40                               0x01000000
236  #define HSR0_VC41                               0x02000000
237  #define HSR0_VC42                               0x04000000
238  #define HSR0_VC43                               0x08000000
239  #define HSR0_VC44                               0x10000000
240  #define HSR0_VC45                               0x20000000
241  #define HSR0_VC46                               0x40000000
242  #define HSR0_VC47                               0x80000000
243  
244  /*
245   *  The following defines are for the flags in the host interrupt control
246   *  register.
247   */
248  #define HICR_IEV                                0x00000001
249  #define HICR_CHGM                               0x00000002
250  
251  /*
252   *  The following defines are for the flags in the DMA status register.
253   */
254  #define DMSR_HP                                 0x00000001
255  #define DMSR_HR                                 0x00000002
256  #define DMSR_SP                                 0x00000004
257  #define DMSR_SR                                 0x00000008
258  
259  /*
260   *  The following defines are for the flags in the host DMA source address
261   *  register.
262   */
263  #define HSAR_HOST_ADDR_MASK                     0xFFFFFFFF
264  #define HSAR_DSP_ADDR_MASK                      0x0000FFFF
265  #define HSAR_MEMID_MASK                         0x000F0000
266  #define HSAR_MEMID_SP_DMEM0                     0x00000000
267  #define HSAR_MEMID_SP_DMEM1                     0x00010000
268  #define HSAR_MEMID_SP_PMEM                      0x00020000
269  #define HSAR_MEMID_SP_DEBUG                     0x00030000
270  #define HSAR_MEMID_OMNI_MEM                     0x000E0000
271  #define HSAR_END                                0x40000000
272  #define HSAR_ERR                                0x80000000
273  
274  /*
275   *  The following defines are for the flags in the host DMA destination address
276   *  register.
277   */
278  #define HDAR_HOST_ADDR_MASK                     0xFFFFFFFF
279  #define HDAR_DSP_ADDR_MASK                      0x0000FFFF
280  #define HDAR_MEMID_MASK                         0x000F0000
281  #define HDAR_MEMID_SP_DMEM0                     0x00000000
282  #define HDAR_MEMID_SP_DMEM1                     0x00010000
283  #define HDAR_MEMID_SP_PMEM                      0x00020000
284  #define HDAR_MEMID_SP_DEBUG                     0x00030000
285  #define HDAR_MEMID_OMNI_MEM                     0x000E0000
286  #define HDAR_END                                0x40000000
287  #define HDAR_ERR                                0x80000000
288  
289  /*
290   *  The following defines are for the flags in the host DMA control register.
291   */
292  #define HDMR_AC_MASK                            0x0000F000
293  #define HDMR_AC_8_16                            0x00001000
294  #define HDMR_AC_M_S                             0x00002000
295  #define HDMR_AC_B_L                             0x00004000
296  #define HDMR_AC_S_U                             0x00008000
297  
298  /*
299   *  The following defines are for the flags in the host DMA control register.
300   */
301  #define HDCR_COUNT_MASK                         0x000003FF
302  #define HDCR_DONE                               0x00004000
303  #define HDCR_OPT                                0x00008000
304  #define HDCR_WBD                                0x00400000
305  #define HDCR_WBS                                0x00800000
306  #define HDCR_DMS_MASK                           0x07000000
307  #define HDCR_DMS_LINEAR                         0x00000000
308  #define HDCR_DMS_16_DWORDS                      0x01000000
309  #define HDCR_DMS_32_DWORDS                      0x02000000
310  #define HDCR_DMS_64_DWORDS                      0x03000000
311  #define HDCR_DMS_128_DWORDS                     0x04000000
312  #define HDCR_DMS_256_DWORDS                     0x05000000
313  #define HDCR_DMS_512_DWORDS                     0x06000000
314  #define HDCR_DMS_1024_DWORDS                    0x07000000
315  #define HDCR_DH                                 0x08000000
316  #define HDCR_SMS_MASK                           0x70000000
317  #define HDCR_SMS_LINEAR                         0x00000000
318  #define HDCR_SMS_16_DWORDS                      0x10000000
319  #define HDCR_SMS_32_DWORDS                      0x20000000
320  #define HDCR_SMS_64_DWORDS                      0x30000000
321  #define HDCR_SMS_128_DWORDS                     0x40000000
322  #define HDCR_SMS_256_DWORDS                     0x50000000
323  #define HDCR_SMS_512_DWORDS                     0x60000000
324  #define HDCR_SMS_1024_DWORDS                    0x70000000
325  #define HDCR_SH                                 0x80000000
326  #define HDCR_COUNT_SHIFT                        0
327  
328  /*
329   *  The following defines are for the flags in the performance monitor control
330   *  register.
331   */
332  #define PFMC_C1SS_MASK                          0x0000001F
333  #define PFMC_C1EV                               0x00000020
334  #define PFMC_C1RS                               0x00008000
335  #define PFMC_C2SS_MASK                          0x001F0000
336  #define PFMC_C2EV                               0x00200000
337  #define PFMC_C2RS                               0x80000000
338  #define PFMC_C1SS_SHIFT                         0
339  #define PFMC_C2SS_SHIFT                         16
340  #define PFMC_BUS_GRANT                          0
341  #define PFMC_GRANT_AFTER_REQ                    1
342  #define PFMC_TRANSACTION                        2
343  #define PFMC_DWORD_TRANSFER                     3
344  #define PFMC_SLAVE_READ                         4
345  #define PFMC_SLAVE_WRITE                        5
346  #define PFMC_PREEMPTION                         6
347  #define PFMC_DISCONNECT_RETRY                   7
348  #define PFMC_INTERRUPT                          8
349  #define PFMC_BUS_OWNERSHIP                      9
350  #define PFMC_TRANSACTION_LAG                    10
351  #define PFMC_PCI_CLOCK                          11
352  #define PFMC_SERIAL_CLOCK                       12
353  #define PFMC_SP_CLOCK                           13
354  
355  /*
356   *  The following defines are for the flags in the performance counter value 1
357   *  register.
358   */
359  #define PFCV1_PC1V_MASK                         0xFFFFFFFF
360  #define PFCV1_PC1V_SHIFT                        0
361  
362  /*
363   *  The following defines are for the flags in the performance counter value 2
364   *  register.
365   */
366  #define PFCV2_PC2V_MASK                         0xFFFFFFFF
367  #define PFCV2_PC2V_SHIFT                        0
368  
369  /*
370   *  The following defines are for the flags in the clock control register 1.
371   */
372  #define CLKCR1_OSCS                             0x00000001
373  #define CLKCR1_OSCP                             0x00000002
374  #define CLKCR1_PLLSS_MASK                       0x0000000C
375  #define CLKCR1_PLLSS_SERIAL                     0x00000000
376  #define CLKCR1_PLLSS_CRYSTAL                    0x00000004
377  #define CLKCR1_PLLSS_PCI                        0x00000008
378  #define CLKCR1_PLLSS_RESERVED                   0x0000000C
379  #define CLKCR1_PLLP                             0x00000010
380  #define CLKCR1_SWCE                             0x00000020
381  #define CLKCR1_PLLOS                            0x00000040
382  
383  /*
384   *  The following defines are for the flags in the clock control register 2.
385   */
386  #define CLKCR2_PDIVS_MASK                       0x0000000F
387  #define CLKCR2_PDIVS_1                          0x00000001
388  #define CLKCR2_PDIVS_2                          0x00000002
389  #define CLKCR2_PDIVS_4                          0x00000004
390  #define CLKCR2_PDIVS_7                          0x00000007
391  #define CLKCR2_PDIVS_8                          0x00000008
392  #define CLKCR2_PDIVS_16                         0x00000000
393  
394  /*
395   *  The following defines are for the flags in the PLL multiplier register.
396   */
397  #define PLLM_MASK                               0x000000FF
398  #define PLLM_SHIFT                              0
399  
400  /*
401   *  The following defines are for the flags in the PLL capacitor coefficient
402   *  register.
403   */
404  #define PLLCC_CDR_MASK                          0x00000007
405  #ifndef NO_CS4610
406  #define PLLCC_CDR_240_350_MHZ                   0x00000000
407  #define PLLCC_CDR_184_265_MHZ                   0x00000001
408  #define PLLCC_CDR_144_205_MHZ                   0x00000002
409  #define PLLCC_CDR_111_160_MHZ                   0x00000003
410  #define PLLCC_CDR_87_123_MHZ                    0x00000004
411  #define PLLCC_CDR_67_96_MHZ                     0x00000005
412  #define PLLCC_CDR_52_74_MHZ                     0x00000006
413  #define PLLCC_CDR_45_58_MHZ                     0x00000007
414  #endif
415  #ifndef NO_CS4612
416  #define PLLCC_CDR_271_398_MHZ                   0x00000000
417  #define PLLCC_CDR_227_330_MHZ                   0x00000001
418  #define PLLCC_CDR_167_239_MHZ                   0x00000002
419  #define PLLCC_CDR_150_215_MHZ                   0x00000003
420  #define PLLCC_CDR_107_154_MHZ                   0x00000004
421  #define PLLCC_CDR_98_140_MHZ                    0x00000005
422  #define PLLCC_CDR_73_104_MHZ                    0x00000006
423  #define PLLCC_CDR_63_90_MHZ                     0x00000007
424  #endif
425  #define PLLCC_LPF_MASK                          0x000000F8
426  #ifndef NO_CS4610
427  #define PLLCC_LPF_23850_60000_KHZ               0x00000000
428  #define PLLCC_LPF_7960_26290_KHZ                0x00000008
429  #define PLLCC_LPF_4160_10980_KHZ                0x00000018
430  #define PLLCC_LPF_1740_4580_KHZ                 0x00000038
431  #define PLLCC_LPF_724_1910_KHZ                  0x00000078
432  #define PLLCC_LPF_317_798_KHZ                   0x000000F8
433  #endif
434  #ifndef NO_CS4612
435  #define PLLCC_LPF_25580_64530_KHZ               0x00000000
436  #define PLLCC_LPF_14360_37270_KHZ               0x00000008
437  #define PLLCC_LPF_6100_16020_KHZ                0x00000018
438  #define PLLCC_LPF_2540_6690_KHZ                 0x00000038
439  #define PLLCC_LPF_1050_2780_KHZ                 0x00000078
440  #define PLLCC_LPF_450_1160_KHZ                  0x000000F8
441  #endif
442  
443  /*
444   *  The following defines are for the flags in the feature reporting register.
445   */
446  #define FRR_FAB_MASK                            0x00000003
447  #define FRR_MASK_MASK                           0x0000001C
448  #ifdef NO_CS4612
449  #define FRR_CFOP_MASK                           0x000000E0
450  #else
451  #define FRR_CFOP_MASK                           0x00000FE0
452  #endif
453  #define FRR_CFOP_NOT_DVD                        0x00000020
454  #define FRR_CFOP_A3D                            0x00000040
455  #define FRR_CFOP_128_PIN                        0x00000080
456  #ifndef NO_CS4612
457  #define FRR_CFOP_CS4280                         0x00000800
458  #endif
459  #define FRR_FAB_SHIFT                           0
460  #define FRR_MASK_SHIFT                          2
461  #define FRR_CFOP_SHIFT                          5
462  
463  /*
464   *  The following defines are for the flags in the configuration load 1
465   *  register.
466   */
467  #define CFL1_CLOCK_SOURCE_MASK                  0x00000003
468  #define CFL1_CLOCK_SOURCE_CS423X                0x00000000
469  #define CFL1_CLOCK_SOURCE_AC97                  0x00000001
470  #define CFL1_CLOCK_SOURCE_CRYSTAL               0x00000002
471  #define CFL1_CLOCK_SOURCE_DUAL_AC97             0x00000003
472  #define CFL1_VALID_DATA_MASK                    0x000000FF
473  
474  /*
475   *  The following defines are for the flags in the configuration load 2
476   *  register.
477   */
478  #define CFL2_VALID_DATA_MASK                    0x000000FF
479  
480  /*
481   *  The following defines are for the flags in the serial port master control
482   *  register 1.
483   */
484  #define SERMC1_MSPE                             0x00000001
485  #define SERMC1_PTC_MASK                         0x0000000E
486  #define SERMC1_PTC_CS423X                       0x00000000
487  #define SERMC1_PTC_AC97                         0x00000002
488  #define SERMC1_PTC_DAC                          0x00000004
489  #define SERMC1_PLB                              0x00000010
490  #define SERMC1_XLB                              0x00000020
491  
492  /*
493   *  The following defines are for the flags in the serial port master control
494   *  register 2.
495   */
496  #define SERMC2_LROE                             0x00000001
497  #define SERMC2_MCOE                             0x00000002
498  #define SERMC2_MCDIV                            0x00000004
499  
500  /*
501   *  The following defines are for the flags in the serial port 1 configuration
502   *  register.
503   */
504  #define SERC1_SO1EN                             0x00000001
505  #define SERC1_SO1F_MASK                         0x0000000E
506  #define SERC1_SO1F_CS423X                       0x00000000
507  #define SERC1_SO1F_AC97                         0x00000002
508  #define SERC1_SO1F_DAC                          0x00000004
509  #define SERC1_SO1F_SPDIF                        0x00000006
510  
511  /*
512   *  The following defines are for the flags in the serial port 2 configuration
513   *  register.
514   */
515  #define SERC2_SI1EN                             0x00000001
516  #define SERC2_SI1F_MASK                         0x0000000E
517  #define SERC2_SI1F_CS423X                       0x00000000
518  #define SERC2_SI1F_AC97                         0x00000002
519  #define SERC2_SI1F_ADC                          0x00000004
520  #define SERC2_SI1F_SPDIF                        0x00000006
521  
522  /*
523   *  The following defines are for the flags in the serial port 3 configuration
524   *  register.
525   */
526  #define SERC3_SO2EN                             0x00000001
527  #define SERC3_SO2F_MASK                         0x00000006
528  #define SERC3_SO2F_DAC                          0x00000000
529  #define SERC3_SO2F_SPDIF                        0x00000002
530  
531  /*
532   *  The following defines are for the flags in the serial port 4 configuration
533   *  register.
534   */
535  #define SERC4_SO3EN                             0x00000001
536  #define SERC4_SO3F_MASK                         0x00000006
537  #define SERC4_SO3F_DAC                          0x00000000
538  #define SERC4_SO3F_SPDIF                        0x00000002
539  
540  /*
541   *  The following defines are for the flags in the serial port 5 configuration
542   *  register.
543   */
544  #define SERC5_SI2EN                             0x00000001
545  #define SERC5_SI2F_MASK                         0x00000006
546  #define SERC5_SI2F_ADC                          0x00000000
547  #define SERC5_SI2F_SPDIF                        0x00000002
548  
549  /*
550   *  The following defines are for the flags in the serial port backdoor sample
551   *  pointer register.
552   */
553  #define SERBSP_FSP_MASK                         0x0000000F
554  #define SERBSP_FSP_SHIFT                        0
555  
556  /*
557   *  The following defines are for the flags in the serial port backdoor status
558   *  register.
559   */
560  #define SERBST_RRDY                             0x00000001
561  #define SERBST_WBSY                             0x00000002
562  
563  /*
564   *  The following defines are for the flags in the serial port backdoor command
565   *  register.
566   */
567  #define SERBCM_RDC                              0x00000001
568  #define SERBCM_WRC                              0x00000002
569  
570  /*
571   *  The following defines are for the flags in the serial port backdoor address
572   *  register.
573   */
574  #ifdef NO_CS4612
575  #define SERBAD_FAD_MASK                         0x000000FF
576  #else
577  #define SERBAD_FAD_MASK                         0x000001FF
578  #endif
579  #define SERBAD_FAD_SHIFT                        0
580  
581  /*
582   *  The following defines are for the flags in the serial port backdoor
583   *  configuration register.
584   */
585  #define SERBCF_HBP                              0x00000001
586  
587  /*
588   *  The following defines are for the flags in the serial port backdoor write
589   *  port register.
590   */
591  #define SERBWP_FWD_MASK                         0x000FFFFF
592  #define SERBWP_FWD_SHIFT                        0
593  
594  /*
595   *  The following defines are for the flags in the serial port backdoor read
596   *  port register.
597   */
598  #define SERBRP_FRD_MASK                         0x000FFFFF
599  #define SERBRP_FRD_SHIFT                        0
600  
601  /*
602   *  The following defines are for the flags in the async FIFO address register.
603   */
604  #ifndef NO_CS4612
605  #define ASER_FADDR_A1_MASK                      0x000001FF
606  #define ASER_FADDR_EN1                          0x00008000
607  #define ASER_FADDR_A2_MASK                      0x01FF0000
608  #define ASER_FADDR_EN2                          0x80000000
609  #define ASER_FADDR_A1_SHIFT                     0
610  #define ASER_FADDR_A2_SHIFT                     16
611  #endif
612  
613  /*
614   *  The following defines are for the flags in the AC97 control register.
615   */
616  #define ACCTL_RSTN                              0x00000001
617  #define ACCTL_ESYN                              0x00000002
618  #define ACCTL_VFRM                              0x00000004
619  #define ACCTL_DCV                               0x00000008
620  #define ACCTL_CRW                               0x00000010
621  #define ACCTL_ASYN                              0x00000020
622  #ifndef NO_CS4612
623  #define ACCTL_TC                                0x00000040
624  #endif
625  
626  /*
627   *  The following defines are for the flags in the AC97 status register.
628   */
629  #define ACSTS_CRDY                              0x00000001
630  #define ACSTS_VSTS                              0x00000002
631  #ifndef NO_CS4612
632  #define ACSTS_WKUP                              0x00000004
633  #endif
634  
635  /*
636   *  The following defines are for the flags in the AC97 output slot valid
637   *  register.
638   */
639  #define ACOSV_SLV3                              0x00000001
640  #define ACOSV_SLV4                              0x00000002
641  #define ACOSV_SLV5                              0x00000004
642  #define ACOSV_SLV6                              0x00000008
643  #define ACOSV_SLV7                              0x00000010
644  #define ACOSV_SLV8                              0x00000020
645  #define ACOSV_SLV9                              0x00000040
646  #define ACOSV_SLV10                             0x00000080
647  #define ACOSV_SLV11                             0x00000100
648  #define ACOSV_SLV12                             0x00000200
649  
650  /*
651   *  The following defines are for the flags in the AC97 command address
652   *  register.
653   */
654  #define ACCAD_CI_MASK                           0x0000007F
655  #define ACCAD_CI_SHIFT                          0
656  
657  /*
658   *  The following defines are for the flags in the AC97 command data register.
659   */
660  #define ACCDA_CD_MASK                           0x0000FFFF
661  #define ACCDA_CD_SHIFT                          0
662  
663  /*
664   *  The following defines are for the flags in the AC97 input slot valid
665   *  register.
666   */
667  #define ACISV_ISV3                              0x00000001
668  #define ACISV_ISV4                              0x00000002
669  #define ACISV_ISV5                              0x00000004
670  #define ACISV_ISV6                              0x00000008
671  #define ACISV_ISV7                              0x00000010
672  #define ACISV_ISV8                              0x00000020
673  #define ACISV_ISV9                              0x00000040
674  #define ACISV_ISV10                             0x00000080
675  #define ACISV_ISV11                             0x00000100
676  #define ACISV_ISV12                             0x00000200
677  
678  /*
679   *  The following defines are for the flags in the AC97 status address
680   *  register.
681   */
682  #define ACSAD_SI_MASK                           0x0000007F
683  #define ACSAD_SI_SHIFT                          0
684  
685  /*
686   *  The following defines are for the flags in the AC97 status data register.
687   */
688  #define ACSDA_SD_MASK                           0x0000FFFF
689  #define ACSDA_SD_SHIFT                          0
690  
691  /*
692   *  The following defines are for the flags in the joystick poll/trigger
693   *  register.
694   */
695  #define JSPT_CAX                                0x00000001
696  #define JSPT_CAY                                0x00000002
697  #define JSPT_CBX                                0x00000004
698  #define JSPT_CBY                                0x00000008
699  #define JSPT_BA1                                0x00000010
700  #define JSPT_BA2                                0x00000020
701  #define JSPT_BB1                                0x00000040
702  #define JSPT_BB2                                0x00000080
703  
704  /*
705   *  The following defines are for the flags in the joystick control register.
706   */
707  #define JSCTL_SP_MASK                           0x00000003
708  #define JSCTL_SP_SLOW                           0x00000000
709  #define JSCTL_SP_MEDIUM_SLOW                    0x00000001
710  #define JSCTL_SP_MEDIUM_FAST                    0x00000002
711  #define JSCTL_SP_FAST                           0x00000003
712  #define JSCTL_ARE                               0x00000004
713  
714  /*
715   *  The following defines are for the flags in the joystick coordinate pair 1
716   *  readback register.
717   */
718  #define JSC1_Y1V_MASK                           0x0000FFFF
719  #define JSC1_X1V_MASK                           0xFFFF0000
720  #define JSC1_Y1V_SHIFT                          0
721  #define JSC1_X1V_SHIFT                          16
722  
723  /*
724   *  The following defines are for the flags in the joystick coordinate pair 2
725   *  readback register.
726   */
727  #define JSC2_Y2V_MASK                           0x0000FFFF
728  #define JSC2_X2V_MASK                           0xFFFF0000
729  #define JSC2_Y2V_SHIFT                          0
730  #define JSC2_X2V_SHIFT                          16
731  
732  /*
733   *  The following defines are for the flags in the MIDI control register.
734   */
735  #define MIDCR_TXE                               0x00000001	/* Enable transmitting. */
736  #define MIDCR_RXE                               0x00000002	/* Enable receiving. */
737  #define MIDCR_RIE                               0x00000004	/* Interrupt upon tx ready. */
738  #define MIDCR_TIE                               0x00000008	/* Interrupt upon rx ready. */
739  #define MIDCR_MLB                               0x00000010	/* Enable midi loopback. */
740  #define MIDCR_MRST                              0x00000020	/* Reset interface. */
741  
742  /*
743   *  The following defines are for the flags in the MIDI status register.
744   */
745  #define MIDSR_TBF                               0x00000001	/* Tx FIFO is full. */
746  #define MIDSR_RBE                               0x00000002	/* Rx FIFO is empty. */
747  
748  /*
749   *  The following defines are for the flags in the MIDI write port register.
750   */
751  #define MIDWP_MWD_MASK                          0x000000FF
752  #define MIDWP_MWD_SHIFT                         0
753  
754  /*
755   *  The following defines are for the flags in the MIDI read port register.
756   */
757  #define MIDRP_MRD_MASK                          0x000000FF
758  #define MIDRP_MRD_SHIFT                         0
759  
760  /*
761   *  The following defines are for the flags in the joystick GPIO register.
762   */
763  #define JSIO_DAX                                0x00000001
764  #define JSIO_DAY                                0x00000002
765  #define JSIO_DBX                                0x00000004
766  #define JSIO_DBY                                0x00000008
767  #define JSIO_AXOE                               0x00000010
768  #define JSIO_AYOE                               0x00000020
769  #define JSIO_BXOE                               0x00000040
770  #define JSIO_BYOE                               0x00000080
771  
772  /*
773   *  The following defines are for the flags in the master async/sync serial
774   *  port enable register.
775   */
776  #ifndef NO_CS4612
777  #define ASER_MASTER_ME                          0x00000001
778  #endif
779  
780  /*
781   *  The following defines are for the flags in the configuration interface
782   *  register.
783   */
784  #define CFGI_CLK                                0x00000001
785  #define CFGI_DOUT                               0x00000002
786  #define CFGI_DIN_EEN                            0x00000004
787  #define CFGI_EELD                               0x00000008
788  
789  /*
790   *  The following defines are for the flags in the subsystem ID and vendor ID
791   *  register.
792   */
793  #define SSVID_VID_MASK                          0x0000FFFF
794  #define SSVID_SID_MASK                          0xFFFF0000
795  #define SSVID_VID_SHIFT                         0
796  #define SSVID_SID_SHIFT                         16
797  
798  /*
799   *  The following defines are for the flags in the GPIO pin interface register.
800   */
801  #define GPIOR_VOLDN                             0x00000001
802  #define GPIOR_VOLUP                             0x00000002
803  #define GPIOR_SI2D                              0x00000004
804  #define GPIOR_SI2OE                             0x00000008
805  
806  /*
807   *  The following defines are for the flags in the extended GPIO pin direction
808   *  register.
809   */
810  #ifndef NO_CS4612
811  #define EGPIODR_GPOE0                           0x00000001
812  #define EGPIODR_GPOE1                           0x00000002
813  #define EGPIODR_GPOE2                           0x00000004
814  #define EGPIODR_GPOE3                           0x00000008
815  #define EGPIODR_GPOE4                           0x00000010
816  #define EGPIODR_GPOE5                           0x00000020
817  #define EGPIODR_GPOE6                           0x00000040
818  #define EGPIODR_GPOE7                           0x00000080
819  #define EGPIODR_GPOE8                           0x00000100
820  #endif
821  
822  /*
823   *  The following defines are for the flags in the extended GPIO pin polarity/
824   *  type register.
825   */
826  #ifndef NO_CS4612
827  #define EGPIOPTR_GPPT0                          0x00000001
828  #define EGPIOPTR_GPPT1                          0x00000002
829  #define EGPIOPTR_GPPT2                          0x00000004
830  #define EGPIOPTR_GPPT3                          0x00000008
831  #define EGPIOPTR_GPPT4                          0x00000010
832  #define EGPIOPTR_GPPT5                          0x00000020
833  #define EGPIOPTR_GPPT6                          0x00000040
834  #define EGPIOPTR_GPPT7                          0x00000080
835  #define EGPIOPTR_GPPT8                          0x00000100
836  #endif
837  
838  /*
839   *  The following defines are for the flags in the extended GPIO pin sticky
840   *  register.
841   */
842  #ifndef NO_CS4612
843  #define EGPIOTR_GPS0                            0x00000001
844  #define EGPIOTR_GPS1                            0x00000002
845  #define EGPIOTR_GPS2                            0x00000004
846  #define EGPIOTR_GPS3                            0x00000008
847  #define EGPIOTR_GPS4                            0x00000010
848  #define EGPIOTR_GPS5                            0x00000020
849  #define EGPIOTR_GPS6                            0x00000040
850  #define EGPIOTR_GPS7                            0x00000080
851  #define EGPIOTR_GPS8                            0x00000100
852  #endif
853  
854  /*
855   *  The following defines are for the flags in the extended GPIO ping wakeup
856   *  register.
857   */
858  #ifndef NO_CS4612
859  #define EGPIOWR_GPW0                            0x00000001
860  #define EGPIOWR_GPW1                            0x00000002
861  #define EGPIOWR_GPW2                            0x00000004
862  #define EGPIOWR_GPW3                            0x00000008
863  #define EGPIOWR_GPW4                            0x00000010
864  #define EGPIOWR_GPW5                            0x00000020
865  #define EGPIOWR_GPW6                            0x00000040
866  #define EGPIOWR_GPW7                            0x00000080
867  #define EGPIOWR_GPW8                            0x00000100
868  #endif
869  
870  /*
871   *  The following defines are for the flags in the extended GPIO pin status
872   *  register.
873   */
874  #ifndef NO_CS4612
875  #define EGPIOSR_GPS0                            0x00000001
876  #define EGPIOSR_GPS1                            0x00000002
877  #define EGPIOSR_GPS2                            0x00000004
878  #define EGPIOSR_GPS3                            0x00000008
879  #define EGPIOSR_GPS4                            0x00000010
880  #define EGPIOSR_GPS5                            0x00000020
881  #define EGPIOSR_GPS6                            0x00000040
882  #define EGPIOSR_GPS7                            0x00000080
883  #define EGPIOSR_GPS8                            0x00000100
884  #endif
885  
886  /*
887   *  The following defines are for the flags in the serial port 6 configuration
888   *  register.
889   */
890  #ifndef NO_CS4612
891  #define SERC6_ASDO2EN                           0x00000001
892  #endif
893  
894  /*
895   *  The following defines are for the flags in the serial port 7 configuration
896   *  register.
897   */
898  #ifndef NO_CS4612
899  #define SERC7_ASDI2EN                           0x00000001
900  #define SERC7_POSILB                            0x00000002
901  #define SERC7_SIPOLB                            0x00000004
902  #define SERC7_SOSILB                            0x00000008
903  #define SERC7_SISOLB                            0x00000010
904  #endif
905  
906  /*
907   *  The following defines are for the flags in the serial port AC link
908   *  configuration register.
909   */
910  #ifndef NO_CS4612
911  #define SERACC_CHIP_TYPE_MASK                  0x00000001
912  #define SERACC_CHIP_TYPE_1_03                  0x00000000
913  #define SERACC_CHIP_TYPE_2_0                   0x00000001
914  #define SERACC_TWO_CODECS                      0x00000002
915  #define SERACC_MDM                             0x00000004
916  #define SERACC_HSP                             0x00000008
917  #define SERACC_ODT                             0x00000010 /* only CS4630 */
918  #endif
919  
920  /*
921   *  The following defines are for the flags in the AC97 control register 2.
922   */
923  #ifndef NO_CS4612
924  #define ACCTL2_RSTN                             0x00000001
925  #define ACCTL2_ESYN                             0x00000002
926  #define ACCTL2_VFRM                             0x00000004
927  #define ACCTL2_DCV                              0x00000008
928  #define ACCTL2_CRW                              0x00000010
929  #define ACCTL2_ASYN                             0x00000020
930  #endif
931  
932  /*
933   *  The following defines are for the flags in the AC97 status register 2.
934   */
935  #ifndef NO_CS4612
936  #define ACSTS2_CRDY                             0x00000001
937  #define ACSTS2_VSTS                             0x00000002
938  #endif
939  
940  /*
941   *  The following defines are for the flags in the AC97 output slot valid
942   *  register 2.
943   */
944  #ifndef NO_CS4612
945  #define ACOSV2_SLV3                             0x00000001
946  #define ACOSV2_SLV4                             0x00000002
947  #define ACOSV2_SLV5                             0x00000004
948  #define ACOSV2_SLV6                             0x00000008
949  #define ACOSV2_SLV7                             0x00000010
950  #define ACOSV2_SLV8                             0x00000020
951  #define ACOSV2_SLV9                             0x00000040
952  #define ACOSV2_SLV10                            0x00000080
953  #define ACOSV2_SLV11                            0x00000100
954  #define ACOSV2_SLV12                            0x00000200
955  #endif
956  
957  /*
958   *  The following defines are for the flags in the AC97 command address
959   *  register 2.
960   */
961  #ifndef NO_CS4612
962  #define ACCAD2_CI_MASK                          0x0000007F
963  #define ACCAD2_CI_SHIFT                         0
964  #endif
965  
966  /*
967   *  The following defines are for the flags in the AC97 command data register
968   *  2.
969   */
970  #ifndef NO_CS4612
971  #define ACCDA2_CD_MASK                          0x0000FFFF
972  #define ACCDA2_CD_SHIFT                         0
973  #endif
974  
975  /*
976   *  The following defines are for the flags in the AC97 input slot valid
977   *  register 2.
978   */
979  #ifndef NO_CS4612
980  #define ACISV2_ISV3                             0x00000001
981  #define ACISV2_ISV4                             0x00000002
982  #define ACISV2_ISV5                             0x00000004
983  #define ACISV2_ISV6                             0x00000008
984  #define ACISV2_ISV7                             0x00000010
985  #define ACISV2_ISV8                             0x00000020
986  #define ACISV2_ISV9                             0x00000040
987  #define ACISV2_ISV10                            0x00000080
988  #define ACISV2_ISV11                            0x00000100
989  #define ACISV2_ISV12                            0x00000200
990  #endif
991  
992  /*
993   *  The following defines are for the flags in the AC97 status address
994   *  register 2.
995   */
996  #ifndef NO_CS4612
997  #define ACSAD2_SI_MASK                          0x0000007F
998  #define ACSAD2_SI_SHIFT                         0
999  #endif
1000  
1001  /*
1002   *  The following defines are for the flags in the AC97 status data register 2.
1003   */
1004  #ifndef NO_CS4612
1005  #define ACSDA2_SD_MASK                          0x0000FFFF
1006  #define ACSDA2_SD_SHIFT                         0
1007  #endif
1008  
1009  /*
1010   *  The following defines are for the flags in the I/O trap address and control
1011   *  registers (all 12).
1012   */
1013  #ifndef NO_CS4612
1014  #define IOTAC_SA_MASK                           0x0000FFFF
1015  #define IOTAC_MSK_MASK                          0x000F0000
1016  #define IOTAC_IODC_MASK                         0x06000000
1017  #define IOTAC_IODC_16_BIT                       0x00000000
1018  #define IOTAC_IODC_10_BIT                       0x02000000
1019  #define IOTAC_IODC_12_BIT                       0x04000000
1020  #define IOTAC_WSPI                              0x08000000
1021  #define IOTAC_RSPI                              0x10000000
1022  #define IOTAC_WSE                               0x20000000
1023  #define IOTAC_WE                                0x40000000
1024  #define IOTAC_RE                                0x80000000
1025  #define IOTAC_SA_SHIFT                          0
1026  #define IOTAC_MSK_SHIFT                         16
1027  #endif
1028  
1029  /*
1030   *  The following defines are for the flags in the I/O trap fast read registers
1031   *  (all 8).
1032   */
1033  #ifndef NO_CS4612
1034  #define IOTFR_D_MASK                            0x0000FFFF
1035  #define IOTFR_A_MASK                            0x000F0000
1036  #define IOTFR_R_MASK                            0x0F000000
1037  #define IOTFR_ALL                               0x40000000
1038  #define IOTFR_VL                                0x80000000
1039  #define IOTFR_D_SHIFT                           0
1040  #define IOTFR_A_SHIFT                           16
1041  #define IOTFR_R_SHIFT                           24
1042  #endif
1043  
1044  /*
1045   *  The following defines are for the flags in the I/O trap FIFO register.
1046   */
1047  #ifndef NO_CS4612
1048  #define IOTFIFO_BA_MASK                         0x00003FFF
1049  #define IOTFIFO_S_MASK                          0x00FF0000
1050  #define IOTFIFO_OF                              0x40000000
1051  #define IOTFIFO_SPIOF                           0x80000000
1052  #define IOTFIFO_BA_SHIFT                        0
1053  #define IOTFIFO_S_SHIFT                         16
1054  #endif
1055  
1056  /*
1057   *  The following defines are for the flags in the I/O trap retry read data
1058   *  register.
1059   */
1060  #ifndef NO_CS4612
1061  #define IOTRRD_D_MASK                           0x0000FFFF
1062  #define IOTRRD_RDV                              0x80000000
1063  #define IOTRRD_D_SHIFT                          0
1064  #endif
1065  
1066  /*
1067   *  The following defines are for the flags in the I/O trap FIFO pointer
1068   *  register.
1069   */
1070  #ifndef NO_CS4612
1071  #define IOTFP_CA_MASK                           0x00003FFF
1072  #define IOTFP_PA_MASK                           0x3FFF0000
1073  #define IOTFP_CA_SHIFT                          0
1074  #define IOTFP_PA_SHIFT                          16
1075  #endif
1076  
1077  /*
1078   *  The following defines are for the flags in the I/O trap control register.
1079   */
1080  #ifndef NO_CS4612
1081  #define IOTCR_ITD                               0x00000001
1082  #define IOTCR_HRV                               0x00000002
1083  #define IOTCR_SRV                               0x00000004
1084  #define IOTCR_DTI                               0x00000008
1085  #define IOTCR_DFI                               0x00000010
1086  #define IOTCR_DDP                               0x00000020
1087  #define IOTCR_JTE                               0x00000040
1088  #define IOTCR_PPE                               0x00000080
1089  #endif
1090  
1091  /*
1092   *  The following defines are for the flags in the direct PCI data register.
1093   */
1094  #ifndef NO_CS4612
1095  #define DPCID_D_MASK                            0xFFFFFFFF
1096  #define DPCID_D_SHIFT                           0
1097  #endif
1098  
1099  /*
1100   *  The following defines are for the flags in the direct PCI address register.
1101   */
1102  #ifndef NO_CS4612
1103  #define DPCIA_A_MASK                            0xFFFFFFFF
1104  #define DPCIA_A_SHIFT                           0
1105  #endif
1106  
1107  /*
1108   *  The following defines are for the flags in the direct PCI command register.
1109   */
1110  #ifndef NO_CS4612
1111  #define DPCIC_C_MASK                            0x0000000F
1112  #define DPCIC_C_IOREAD                          0x00000002
1113  #define DPCIC_C_IOWRITE                         0x00000003
1114  #define DPCIC_BE_MASK                           0x000000F0
1115  #endif
1116  
1117  /*
1118   *  The following defines are for the flags in the PC/PCI request register.
1119   */
1120  #ifndef NO_CS4612
1121  #define PCPCIR_RDC_MASK                         0x00000007
1122  #define PCPCIR_C_MASK                           0x00007000
1123  #define PCPCIR_REQ                              0x00008000
1124  #define PCPCIR_RDC_SHIFT                        0
1125  #define PCPCIR_C_SHIFT                          12
1126  #endif
1127  
1128  /*
1129   *  The following defines are for the flags in the PC/PCI grant register.
1130   */
1131  #ifndef NO_CS4612
1132  #define PCPCIG_GDC_MASK                         0x00000007
1133  #define PCPCIG_VL                               0x00008000
1134  #define PCPCIG_GDC_SHIFT                        0
1135  #endif
1136  
1137  /*
1138   *  The following defines are for the flags in the PC/PCI master enable
1139   *  register.
1140   */
1141  #ifndef NO_CS4612
1142  #define PCPCIEN_EN                              0x00000001
1143  #endif
1144  
1145  /*
1146   *  The following defines are for the flags in the extended PCI power
1147   *  management control register.
1148   */
1149  #ifndef NO_CS4612
1150  #define EPCIPMC_GWU                             0x00000001
1151  #define EPCIPMC_FSPC                            0x00000002
1152  #endif
1153  
1154  /*
1155   *  The following defines are for the flags in the SP control register.
1156   */
1157  #define SPCR_RUN                                0x00000001
1158  #define SPCR_STPFR                              0x00000002
1159  #define SPCR_RUNFR                              0x00000004
1160  #define SPCR_TICK                               0x00000008
1161  #define SPCR_DRQEN                              0x00000020
1162  #define SPCR_RSTSP                              0x00000040
1163  #define SPCR_OREN                               0x00000080
1164  #ifndef NO_CS4612
1165  #define SPCR_PCIINT                             0x00000100
1166  #define SPCR_OINTD                              0x00000200
1167  #define SPCR_CRE                                0x00008000
1168  #endif
1169  
1170  /*
1171   *  The following defines are for the flags in the debug index register.
1172   */
1173  #define DREG_REGID_MASK                         0x0000007F
1174  #define DREG_DEBUG                              0x00000080
1175  #define DREG_RGBK_MASK                          0x00000700
1176  #define DREG_TRAP                               0x00000800
1177  #if !defined(NO_CS4612)
1178  #if !defined(NO_CS4615)
1179  #define DREG_TRAPX                              0x00001000
1180  #endif
1181  #endif
1182  #define DREG_REGID_SHIFT                        0
1183  #define DREG_RGBK_SHIFT                         8
1184  #define DREG_RGBK_REGID_MASK                    0x0000077F
1185  #define DREG_REGID_R0                           0x00000010
1186  #define DREG_REGID_R1                           0x00000011
1187  #define DREG_REGID_R2                           0x00000012
1188  #define DREG_REGID_R3                           0x00000013
1189  #define DREG_REGID_R4                           0x00000014
1190  #define DREG_REGID_R5                           0x00000015
1191  #define DREG_REGID_R6                           0x00000016
1192  #define DREG_REGID_R7                           0x00000017
1193  #define DREG_REGID_R8                           0x00000018
1194  #define DREG_REGID_R9                           0x00000019
1195  #define DREG_REGID_RA                           0x0000001A
1196  #define DREG_REGID_RB                           0x0000001B
1197  #define DREG_REGID_RC                           0x0000001C
1198  #define DREG_REGID_RD                           0x0000001D
1199  #define DREG_REGID_RE                           0x0000001E
1200  #define DREG_REGID_RF                           0x0000001F
1201  #define DREG_REGID_RA_BUS_LOW                   0x00000020
1202  #define DREG_REGID_RA_BUS_HIGH                  0x00000038
1203  #define DREG_REGID_YBUS_LOW                     0x00000050
1204  #define DREG_REGID_YBUS_HIGH                    0x00000058
1205  #define DREG_REGID_TRAP_0                       0x00000100
1206  #define DREG_REGID_TRAP_1                       0x00000101
1207  #define DREG_REGID_TRAP_2                       0x00000102
1208  #define DREG_REGID_TRAP_3                       0x00000103
1209  #define DREG_REGID_TRAP_4                       0x00000104
1210  #define DREG_REGID_TRAP_5                       0x00000105
1211  #define DREG_REGID_TRAP_6                       0x00000106
1212  #define DREG_REGID_TRAP_7                       0x00000107
1213  #define DREG_REGID_INDIRECT_ADDRESS             0x0000010E
1214  #define DREG_REGID_TOP_OF_STACK                 0x0000010F
1215  #if !defined(NO_CS4612)
1216  #if !defined(NO_CS4615)
1217  #define DREG_REGID_TRAP_8                       0x00000110
1218  #define DREG_REGID_TRAP_9                       0x00000111
1219  #define DREG_REGID_TRAP_10                      0x00000112
1220  #define DREG_REGID_TRAP_11                      0x00000113
1221  #define DREG_REGID_TRAP_12                      0x00000114
1222  #define DREG_REGID_TRAP_13                      0x00000115
1223  #define DREG_REGID_TRAP_14                      0x00000116
1224  #define DREG_REGID_TRAP_15                      0x00000117
1225  #define DREG_REGID_TRAP_16                      0x00000118
1226  #define DREG_REGID_TRAP_17                      0x00000119
1227  #define DREG_REGID_TRAP_18                      0x0000011A
1228  #define DREG_REGID_TRAP_19                      0x0000011B
1229  #define DREG_REGID_TRAP_20                      0x0000011C
1230  #define DREG_REGID_TRAP_21                      0x0000011D
1231  #define DREG_REGID_TRAP_22                      0x0000011E
1232  #define DREG_REGID_TRAP_23                      0x0000011F
1233  #endif
1234  #endif
1235  #define DREG_REGID_RSA0_LOW                     0x00000200
1236  #define DREG_REGID_RSA0_HIGH                    0x00000201
1237  #define DREG_REGID_RSA1_LOW                     0x00000202
1238  #define DREG_REGID_RSA1_HIGH                    0x00000203
1239  #define DREG_REGID_RSA2                         0x00000204
1240  #define DREG_REGID_RSA3                         0x00000205
1241  #define DREG_REGID_RSI0_LOW                     0x00000206
1242  #define DREG_REGID_RSI0_HIGH                    0x00000207
1243  #define DREG_REGID_RSI1                         0x00000208
1244  #define DREG_REGID_RSI2                         0x00000209
1245  #define DREG_REGID_SAGUSTATUS                   0x0000020A
1246  #define DREG_REGID_RSCONFIG01_LOW               0x0000020B
1247  #define DREG_REGID_RSCONFIG01_HIGH              0x0000020C
1248  #define DREG_REGID_RSCONFIG23_LOW               0x0000020D
1249  #define DREG_REGID_RSCONFIG23_HIGH              0x0000020E
1250  #define DREG_REGID_RSDMA01E                     0x0000020F
1251  #define DREG_REGID_RSDMA23E                     0x00000210
1252  #define DREG_REGID_RSD0_LOW                     0x00000211
1253  #define DREG_REGID_RSD0_HIGH                    0x00000212
1254  #define DREG_REGID_RSD1_LOW                     0x00000213
1255  #define DREG_REGID_RSD1_HIGH                    0x00000214
1256  #define DREG_REGID_RSD2_LOW                     0x00000215
1257  #define DREG_REGID_RSD2_HIGH                    0x00000216
1258  #define DREG_REGID_RSD3_LOW                     0x00000217
1259  #define DREG_REGID_RSD3_HIGH                    0x00000218
1260  #define DREG_REGID_SRAR_HIGH                    0x0000021A
1261  #define DREG_REGID_SRAR_LOW                     0x0000021B
1262  #define DREG_REGID_DMA_STATE                    0x0000021C
1263  #define DREG_REGID_CURRENT_DMA_STREAM           0x0000021D
1264  #define DREG_REGID_NEXT_DMA_STREAM              0x0000021E
1265  #define DREG_REGID_CPU_STATUS                   0x00000300
1266  #define DREG_REGID_MAC_MODE                     0x00000301
1267  #define DREG_REGID_STACK_AND_REPEAT             0x00000302
1268  #define DREG_REGID_INDEX0                       0x00000304
1269  #define DREG_REGID_INDEX1                       0x00000305
1270  #define DREG_REGID_DMA_STATE_0_3                0x00000400
1271  #define DREG_REGID_DMA_STATE_4_7                0x00000404
1272  #define DREG_REGID_DMA_STATE_8_11               0x00000408
1273  #define DREG_REGID_DMA_STATE_12_15              0x0000040C
1274  #define DREG_REGID_DMA_STATE_16_19              0x00000410
1275  #define DREG_REGID_DMA_STATE_20_23              0x00000414
1276  #define DREG_REGID_DMA_STATE_24_27              0x00000418
1277  #define DREG_REGID_DMA_STATE_28_31              0x0000041C
1278  #define DREG_REGID_DMA_STATE_32_35              0x00000420
1279  #define DREG_REGID_DMA_STATE_36_39              0x00000424
1280  #define DREG_REGID_DMA_STATE_40_43              0x00000428
1281  #define DREG_REGID_DMA_STATE_44_47              0x0000042C
1282  #define DREG_REGID_DMA_STATE_48_51              0x00000430
1283  #define DREG_REGID_DMA_STATE_52_55              0x00000434
1284  #define DREG_REGID_DMA_STATE_56_59              0x00000438
1285  #define DREG_REGID_DMA_STATE_60_63              0x0000043C
1286  #define DREG_REGID_DMA_STATE_64_67              0x00000440
1287  #define DREG_REGID_DMA_STATE_68_71              0x00000444
1288  #define DREG_REGID_DMA_STATE_72_75              0x00000448
1289  #define DREG_REGID_DMA_STATE_76_79              0x0000044C
1290  #define DREG_REGID_DMA_STATE_80_83              0x00000450
1291  #define DREG_REGID_DMA_STATE_84_87              0x00000454
1292  #define DREG_REGID_DMA_STATE_88_91              0x00000458
1293  #define DREG_REGID_DMA_STATE_92_95              0x0000045C
1294  #define DREG_REGID_TRAP_SELECT                  0x00000500
1295  #define DREG_REGID_TRAP_WRITE_0                 0x00000500
1296  #define DREG_REGID_TRAP_WRITE_1                 0x00000501
1297  #define DREG_REGID_TRAP_WRITE_2                 0x00000502
1298  #define DREG_REGID_TRAP_WRITE_3                 0x00000503
1299  #define DREG_REGID_TRAP_WRITE_4                 0x00000504
1300  #define DREG_REGID_TRAP_WRITE_5                 0x00000505
1301  #define DREG_REGID_TRAP_WRITE_6                 0x00000506
1302  #define DREG_REGID_TRAP_WRITE_7                 0x00000507
1303  #if !defined(NO_CS4612)
1304  #if !defined(NO_CS4615)
1305  #define DREG_REGID_TRAP_WRITE_8                 0x00000510
1306  #define DREG_REGID_TRAP_WRITE_9                 0x00000511
1307  #define DREG_REGID_TRAP_WRITE_10                0x00000512
1308  #define DREG_REGID_TRAP_WRITE_11                0x00000513
1309  #define DREG_REGID_TRAP_WRITE_12                0x00000514
1310  #define DREG_REGID_TRAP_WRITE_13                0x00000515
1311  #define DREG_REGID_TRAP_WRITE_14                0x00000516
1312  #define DREG_REGID_TRAP_WRITE_15                0x00000517
1313  #define DREG_REGID_TRAP_WRITE_16                0x00000518
1314  #define DREG_REGID_TRAP_WRITE_17                0x00000519
1315  #define DREG_REGID_TRAP_WRITE_18                0x0000051A
1316  #define DREG_REGID_TRAP_WRITE_19                0x0000051B
1317  #define DREG_REGID_TRAP_WRITE_20                0x0000051C
1318  #define DREG_REGID_TRAP_WRITE_21                0x0000051D
1319  #define DREG_REGID_TRAP_WRITE_22                0x0000051E
1320  #define DREG_REGID_TRAP_WRITE_23                0x0000051F
1321  #endif
1322  #endif
1323  #define DREG_REGID_MAC0_ACC0_LOW                0x00000600
1324  #define DREG_REGID_MAC0_ACC1_LOW                0x00000601
1325  #define DREG_REGID_MAC0_ACC2_LOW                0x00000602
1326  #define DREG_REGID_MAC0_ACC3_LOW                0x00000603
1327  #define DREG_REGID_MAC1_ACC0_LOW                0x00000604
1328  #define DREG_REGID_MAC1_ACC1_LOW                0x00000605
1329  #define DREG_REGID_MAC1_ACC2_LOW                0x00000606
1330  #define DREG_REGID_MAC1_ACC3_LOW                0x00000607
1331  #define DREG_REGID_MAC0_ACC0_MID                0x00000608
1332  #define DREG_REGID_MAC0_ACC1_MID                0x00000609
1333  #define DREG_REGID_MAC0_ACC2_MID                0x0000060A
1334  #define DREG_REGID_MAC0_ACC3_MID                0x0000060B
1335  #define DREG_REGID_MAC1_ACC0_MID                0x0000060C
1336  #define DREG_REGID_MAC1_ACC1_MID                0x0000060D
1337  #define DREG_REGID_MAC1_ACC2_MID                0x0000060E
1338  #define DREG_REGID_MAC1_ACC3_MID                0x0000060F
1339  #define DREG_REGID_MAC0_ACC0_HIGH               0x00000610
1340  #define DREG_REGID_MAC0_ACC1_HIGH               0x00000611
1341  #define DREG_REGID_MAC0_ACC2_HIGH               0x00000612
1342  #define DREG_REGID_MAC0_ACC3_HIGH               0x00000613
1343  #define DREG_REGID_MAC1_ACC0_HIGH               0x00000614
1344  #define DREG_REGID_MAC1_ACC1_HIGH               0x00000615
1345  #define DREG_REGID_MAC1_ACC2_HIGH               0x00000616
1346  #define DREG_REGID_MAC1_ACC3_HIGH               0x00000617
1347  #define DREG_REGID_RSHOUT_LOW                   0x00000620
1348  #define DREG_REGID_RSHOUT_MID                   0x00000628
1349  #define DREG_REGID_RSHOUT_HIGH                  0x00000630
1350  
1351  /*
1352   *  The following defines are for the flags in the DMA stream requestor write
1353   */
1354  #define DSRWP_DSR_MASK                          0x0000000F
1355  #define DSRWP_DSR_BG_RQ                         0x00000001
1356  #define DSRWP_DSR_PRIORITY_MASK                 0x00000006
1357  #define DSRWP_DSR_PRIORITY_0                    0x00000000
1358  #define DSRWP_DSR_PRIORITY_1                    0x00000002
1359  #define DSRWP_DSR_PRIORITY_2                    0x00000004
1360  #define DSRWP_DSR_PRIORITY_3                    0x00000006
1361  #define DSRWP_DSR_RQ_PENDING                    0x00000008
1362  
1363  /*
1364   *  The following defines are for the flags in the trap write port register.
1365   */
1366  #define TWPR_TW_MASK                            0x0000FFFF
1367  #define TWPR_TW_SHIFT                           0
1368  
1369  /*
1370   *  The following defines are for the flags in the stack pointer write
1371   *  register.
1372   */
1373  #define SPWR_STKP_MASK                          0x0000000F
1374  #define SPWR_STKP_SHIFT                         0
1375  
1376  /*
1377   *  The following defines are for the flags in the SP interrupt register.
1378   */
1379  #define SPIR_FRI                                0x00000001
1380  #define SPIR_DOI                                0x00000002
1381  #define SPIR_GPI2                               0x00000004
1382  #define SPIR_GPI3                               0x00000008
1383  #define SPIR_IP0                                0x00000010
1384  #define SPIR_IP1                                0x00000020
1385  #define SPIR_IP2                                0x00000040
1386  #define SPIR_IP3                                0x00000080
1387  
1388  /*
1389   *  The following defines are for the flags in the functional group 1 register.
1390   */
1391  #define FGR1_F1S_MASK                           0x0000FFFF
1392  #define FGR1_F1S_SHIFT                          0
1393  
1394  /*
1395   *  The following defines are for the flags in the SP clock status register.
1396   */
1397  #define SPCS_FRI                                0x00000001
1398  #define SPCS_DOI                                0x00000002
1399  #define SPCS_GPI2                               0x00000004
1400  #define SPCS_GPI3                               0x00000008
1401  #define SPCS_IP0                                0x00000010
1402  #define SPCS_IP1                                0x00000020
1403  #define SPCS_IP2                                0x00000040
1404  #define SPCS_IP3                                0x00000080
1405  #define SPCS_SPRUN                              0x00000100
1406  #define SPCS_SLEEP                              0x00000200
1407  #define SPCS_FG                                 0x00000400
1408  #define SPCS_ORUN                               0x00000800
1409  #define SPCS_IRQ                                0x00001000
1410  #define SPCS_FGN_MASK                           0x0000E000
1411  #define SPCS_FGN_SHIFT                          13
1412  
1413  /*
1414   *  The following defines are for the flags in the SP DMA requestor status
1415   *  register.
1416   */
1417  #define SDSR_DCS_MASK                           0x000000FF
1418  #define SDSR_DCS_SHIFT                          0
1419  #define SDSR_DCS_NONE                           0x00000007
1420  
1421  /*
1422   *  The following defines are for the flags in the frame timer register.
1423   */
1424  #define FRMT_FTV_MASK                           0x0000FFFF
1425  #define FRMT_FTV_SHIFT                          0
1426  
1427  /*
1428   *  The following defines are for the flags in the frame timer current count
1429   *  register.
1430   */
1431  #define FRCC_FCC_MASK                           0x0000FFFF
1432  #define FRCC_FCC_SHIFT                          0
1433  
1434  /*
1435   *  The following defines are for the flags in the frame timer save count
1436   *  register.
1437   */
1438  #define FRSC_FCS_MASK                           0x0000FFFF
1439  #define FRSC_FCS_SHIFT                          0
1440  
1441  /*
1442   *  The following define the various flags stored in the scatter/gather
1443   *  descriptors.
1444   */
1445  #define DMA_SG_NEXT_ENTRY_MASK                  0x00000FF8
1446  #define DMA_SG_SAMPLE_END_MASK                  0x0FFF0000
1447  #define DMA_SG_SAMPLE_END_FLAG                  0x10000000
1448  #define DMA_SG_LOOP_END_FLAG                    0x20000000
1449  #define DMA_SG_SIGNAL_END_FLAG                  0x40000000
1450  #define DMA_SG_SIGNAL_PAGE_FLAG                 0x80000000
1451  #define DMA_SG_NEXT_ENTRY_SHIFT                 3
1452  #define DMA_SG_SAMPLE_END_SHIFT                 16
1453  
1454  /*
1455   *  The following define the offsets of the fields within the on-chip generic
1456   *  DMA requestor.
1457   */
1458  #define DMA_RQ_CONTROL1                         0x00000000
1459  #define DMA_RQ_CONTROL2                         0x00000004
1460  #define DMA_RQ_SOURCE_ADDR                      0x00000008
1461  #define DMA_RQ_DESTINATION_ADDR                 0x0000000C
1462  #define DMA_RQ_NEXT_PAGE_ADDR                   0x00000010
1463  #define DMA_RQ_NEXT_PAGE_SGDESC                 0x00000014
1464  #define DMA_RQ_LOOP_START_ADDR                  0x00000018
1465  #define DMA_RQ_POST_LOOP_ADDR                   0x0000001C
1466  #define DMA_RQ_PAGE_MAP_ADDR                    0x00000020
1467  
1468  /*
1469   *  The following defines are for the flags in the first control word of the
1470   *  on-chip generic DMA requestor.
1471   */
1472  #define DMA_RQ_C1_COUNT_MASK                    0x000003FF
1473  #define DMA_RQ_C1_DESTINATION_SCATTER           0x00001000
1474  #define DMA_RQ_C1_SOURCE_GATHER                 0x00002000
1475  #define DMA_RQ_C1_DONE_FLAG                     0x00004000
1476  #define DMA_RQ_C1_OPTIMIZE_STATE                0x00008000
1477  #define DMA_RQ_C1_SAMPLE_END_STATE_MASK         0x00030000
1478  #define DMA_RQ_C1_FULL_PAGE                     0x00000000
1479  #define DMA_RQ_C1_BEFORE_SAMPLE_END             0x00010000
1480  #define DMA_RQ_C1_PAGE_MAP_ERROR                0x00020000
1481  #define DMA_RQ_C1_AT_SAMPLE_END                 0x00030000
1482  #define DMA_RQ_C1_LOOP_END_STATE_MASK           0x000C0000
1483  #define DMA_RQ_C1_NOT_LOOP_END                  0x00000000
1484  #define DMA_RQ_C1_BEFORE_LOOP_END               0x00040000
1485  #define DMA_RQ_C1_2PAGE_LOOP_BEGIN              0x00080000
1486  #define DMA_RQ_C1_LOOP_BEGIN                    0x000C0000
1487  #define DMA_RQ_C1_PAGE_MAP_MASK                 0x00300000
1488  #define DMA_RQ_C1_PM_NONE_PENDING               0x00000000
1489  #define DMA_RQ_C1_PM_NEXT_PENDING               0x00100000
1490  #define DMA_RQ_C1_PM_RESERVED                   0x00200000
1491  #define DMA_RQ_C1_PM_LOOP_NEXT_PENDING          0x00300000
1492  #define DMA_RQ_C1_WRITEBACK_DEST_FLAG           0x00400000
1493  #define DMA_RQ_C1_WRITEBACK_SRC_FLAG            0x00800000
1494  #define DMA_RQ_C1_DEST_SIZE_MASK                0x07000000
1495  #define DMA_RQ_C1_DEST_LINEAR                   0x00000000
1496  #define DMA_RQ_C1_DEST_MOD16                    0x01000000
1497  #define DMA_RQ_C1_DEST_MOD32                    0x02000000
1498  #define DMA_RQ_C1_DEST_MOD64                    0x03000000
1499  #define DMA_RQ_C1_DEST_MOD128                   0x04000000
1500  #define DMA_RQ_C1_DEST_MOD256                   0x05000000
1501  #define DMA_RQ_C1_DEST_MOD512                   0x06000000
1502  #define DMA_RQ_C1_DEST_MOD1024                  0x07000000
1503  #define DMA_RQ_C1_DEST_ON_HOST                  0x08000000
1504  #define DMA_RQ_C1_SOURCE_SIZE_MASK              0x70000000
1505  #define DMA_RQ_C1_SOURCE_LINEAR                 0x00000000
1506  #define DMA_RQ_C1_SOURCE_MOD16                  0x10000000
1507  #define DMA_RQ_C1_SOURCE_MOD32                  0x20000000
1508  #define DMA_RQ_C1_SOURCE_MOD64                  0x30000000
1509  #define DMA_RQ_C1_SOURCE_MOD128                 0x40000000
1510  #define DMA_RQ_C1_SOURCE_MOD256                 0x50000000
1511  #define DMA_RQ_C1_SOURCE_MOD512                 0x60000000
1512  #define DMA_RQ_C1_SOURCE_MOD1024                0x70000000
1513  #define DMA_RQ_C1_SOURCE_ON_HOST                0x80000000
1514  #define DMA_RQ_C1_COUNT_SHIFT                   0
1515  
1516  /*
1517   *  The following defines are for the flags in the second control word of the
1518   *  on-chip generic DMA requestor.
1519   */
1520  #define DMA_RQ_C2_VIRTUAL_CHANNEL_MASK          0x0000003F
1521  #define DMA_RQ_C2_VIRTUAL_SIGNAL_MASK           0x00000300
1522  #define DMA_RQ_C2_NO_VIRTUAL_SIGNAL             0x00000000
1523  #define DMA_RQ_C2_SIGNAL_EVERY_DMA              0x00000100
1524  #define DMA_RQ_C2_SIGNAL_SOURCE_PINGPONG        0x00000200
1525  #define DMA_RQ_C2_SIGNAL_DEST_PINGPONG          0x00000300
1526  #define DMA_RQ_C2_AUDIO_CONVERT_MASK            0x0000F000
1527  #define DMA_RQ_C2_AC_NONE                       0x00000000
1528  #define DMA_RQ_C2_AC_8_TO_16_BIT                0x00001000
1529  #define DMA_RQ_C2_AC_MONO_TO_STEREO             0x00002000
1530  #define DMA_RQ_C2_AC_ENDIAN_CONVERT             0x00004000
1531  #define DMA_RQ_C2_AC_SIGNED_CONVERT             0x00008000
1532  #define DMA_RQ_C2_LOOP_END_MASK                 0x0FFF0000
1533  #define DMA_RQ_C2_LOOP_MASK                     0x30000000
1534  #define DMA_RQ_C2_NO_LOOP                       0x00000000
1535  #define DMA_RQ_C2_ONE_PAGE_LOOP                 0x10000000
1536  #define DMA_RQ_C2_TWO_PAGE_LOOP                 0x20000000
1537  #define DMA_RQ_C2_MULTI_PAGE_LOOP               0x30000000
1538  #define DMA_RQ_C2_SIGNAL_LOOP_BACK              0x40000000
1539  #define DMA_RQ_C2_SIGNAL_POST_BEGIN_PAGE        0x80000000
1540  #define DMA_RQ_C2_VIRTUAL_CHANNEL_SHIFT         0
1541  #define DMA_RQ_C2_LOOP_END_SHIFT                16
1542  
1543  /*
1544   *  The following defines are for the flags in the source and destination words
1545   *  of the on-chip generic DMA requestor.
1546   */
1547  #define DMA_RQ_SD_ADDRESS_MASK                  0x0000FFFF
1548  #define DMA_RQ_SD_MEMORY_ID_MASK                0x000F0000
1549  #define DMA_RQ_SD_SP_PARAM_ADDR                 0x00000000
1550  #define DMA_RQ_SD_SP_SAMPLE_ADDR                0x00010000
1551  #define DMA_RQ_SD_SP_PROGRAM_ADDR               0x00020000
1552  #define DMA_RQ_SD_SP_DEBUG_ADDR                 0x00030000
1553  #define DMA_RQ_SD_OMNIMEM_ADDR                  0x000E0000
1554  #define DMA_RQ_SD_END_FLAG                      0x40000000
1555  #define DMA_RQ_SD_ERROR_FLAG                    0x80000000
1556  #define DMA_RQ_SD_ADDRESS_SHIFT                 0
1557  
1558  /*
1559   *  The following defines are for the flags in the page map address word of the
1560   *  on-chip generic DMA requestor.
1561   */
1562  #define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_MASK   0x00000FF8
1563  #define DMA_RQ_PMA_PAGE_TABLE_MASK              0xFFFFF000
1564  #define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_SHIFT  3
1565  #define DMA_RQ_PMA_PAGE_TABLE_SHIFT             12
1566  
1567  #define BA1_VARIDEC_BUF_1       0x000
1568  
1569  #define BA1_PDTC                0x0c0    /* BA1_PLAY_DMA_TRANSACTION_COUNT_REG */
1570  #define BA1_PFIE                0x0c4    /* BA1_PLAY_FORMAT_&_INTERRUPT_ENABLE_REG */
1571  #define BA1_PBA                 0x0c8    /* BA1_PLAY_BUFFER_ADDRESS */
1572  #define BA1_PVOL                0x0f8    /* BA1_PLAY_VOLUME_REG */
1573  #define BA1_PSRC                0x288    /* BA1_PLAY_SAMPLE_RATE_CORRECTION_REG */
1574  #define BA1_PCTL                0x2a4    /* BA1_PLAY_CONTROL_REG */
1575  #define BA1_PPI                 0x2b4    /* BA1_PLAY_PHASE_INCREMENT_REG */
1576  
1577  #define BA1_CCTL                0x064    /* BA1_CAPTURE_CONTROL_REG */
1578  #define BA1_CIE                 0x104    /* BA1_CAPTURE_INTERRUPT_ENABLE_REG */
1579  #define BA1_CBA                 0x10c    /* BA1_CAPTURE_BUFFER_ADDRESS */
1580  #define BA1_CSRC                0x2c8    /* BA1_CAPTURE_SAMPLE_RATE_CORRECTION_REG */
1581  #define BA1_CCI                 0x2d8    /* BA1_CAPTURE_COEFFICIENT_INCREMENT_REG */
1582  #define BA1_CD                  0x2e0    /* BA1_CAPTURE_DELAY_REG */
1583  #define BA1_CPI                 0x2f4    /* BA1_CAPTURE_PHASE_INCREMENT_REG */
1584  #define BA1_CVOL                0x2f8    /* BA1_CAPTURE_VOLUME_REG */
1585  
1586  #define BA1_CFG1                0x134    /* BA1_CAPTURE_FRAME_GROUP_1_REG */
1587  #define BA1_CFG2                0x138    /* BA1_CAPTURE_FRAME_GROUP_2_REG */
1588  #define BA1_CCST                0x13c    /* BA1_CAPTURE_CONSTANT_REG */
1589  #define BA1_CSPB                0x340    /* BA1_CAPTURE_SPB_ADDRESS */
1590  
1591  /*
1592   *
1593   */
1594  
1595  #define CS46XX_MODE_OUTPUT	(1<<0)	 /* MIDI UART - output */
1596  #define CS46XX_MODE_INPUT	(1<<1)	 /* MIDI UART - input */
1597  
1598  /*
1599   *
1600   */
1601  
1602  #define SAVE_REG_MAX             0x10
1603  #define POWER_DOWN_ALL         0x7f0f
1604  
1605  /* maxinum number of AC97 codecs connected, AC97 2.0 defined 4 */
1606  #define MAX_NR_AC97				            4
1607  #define CS46XX_PRIMARY_CODEC_INDEX          0
1608  #define CS46XX_SECONDARY_CODEC_INDEX		1
1609  #define CS46XX_SECONDARY_CODEC_OFFSET		0x80
1610  #define CS46XX_DSP_CAPTURE_CHANNEL          1
1611  
1612  /* capture */
1613  #define CS46XX_DSP_CAPTURE_CHANNEL          1
1614  
1615  /* mixer */
1616  #define CS46XX_MIXER_SPDIF_INPUT_ELEMENT    1
1617  #define CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT   2
1618  
1619  
1620  struct snd_cs46xx_pcm {
1621  	struct snd_dma_buffer hw_buf;
1622  
1623  	unsigned int ctl;
1624  	unsigned int shift;	/* Shift count to trasform frames in bytes */
1625  	struct snd_pcm_indirect pcm_rec;
1626  	struct snd_pcm_substream *substream;
1627  
1628  	struct dsp_pcm_channel_descriptor * pcm_channel;
1629  
1630  	int pcm_channel_id;    /* Fron Rear, Center Lfe  ... */
1631  };
1632  
1633  struct snd_cs46xx_region {
1634  	char name[24];
1635  	unsigned long base;
1636  	void __iomem *remap_addr;
1637  	unsigned long size;
1638  	struct resource *resource;
1639  };
1640  
1641  struct snd_cs46xx {
1642  	int irq;
1643  	unsigned long ba0_addr;
1644  	unsigned long ba1_addr;
1645  	union {
1646  		struct {
1647  			struct snd_cs46xx_region ba0;
1648  			struct snd_cs46xx_region data0;
1649  			struct snd_cs46xx_region data1;
1650  			struct snd_cs46xx_region pmem;
1651  			struct snd_cs46xx_region reg;
1652  		} name;
1653  		struct snd_cs46xx_region idx[5];
1654  	} region;
1655  
1656  	unsigned int mode;
1657  
1658  	struct {
1659  		struct snd_dma_buffer hw_buf;
1660  
1661  		unsigned int ctl;
1662  		unsigned int shift;	/* Shift count to trasform frames in bytes */
1663  		struct snd_pcm_indirect pcm_rec;
1664  		struct snd_pcm_substream *substream;
1665  	} capt;
1666  
1667  
1668  	int nr_ac97_codecs;
1669  	struct snd_ac97_bus *ac97_bus;
1670  	struct snd_ac97 *ac97[MAX_NR_AC97];
1671  
1672  	struct pci_dev *pci;
1673  	struct snd_card *card;
1674  	struct snd_pcm *pcm;
1675  
1676  	struct snd_rawmidi *rmidi;
1677  	struct snd_rawmidi_substream *midi_input;
1678  	struct snd_rawmidi_substream *midi_output;
1679  
1680  	spinlock_t reg_lock;
1681  	unsigned int midcr;
1682  	unsigned int uartm;
1683  
1684  	int amplifier;
1685  	void (*amplifier_ctrl)(struct snd_cs46xx *, int);
1686  	void (*active_ctrl)(struct snd_cs46xx *, int);
1687    	void (*mixer_init)(struct snd_cs46xx *);
1688  
1689  	int acpi_port;
1690  	struct snd_kcontrol *eapd_switch; /* for amplifier hack */
1691  	int accept_valid;	/* accept mmap valid (for OSS) */
1692  	int in_suspend;
1693  
1694  	struct gameport *gameport;
1695  
1696  #ifdef CONFIG_SND_CS46XX_NEW_DSP
1697  	struct mutex spos_mutex;
1698  
1699  	struct dsp_spos_instance * dsp_spos_instance;
1700  
1701  	struct snd_pcm *pcm_rear;
1702  	struct snd_pcm *pcm_center_lfe;
1703  	struct snd_pcm *pcm_iec958;
1704  
1705  #define CS46XX_DSP_MODULES	5
1706  	struct dsp_module_desc *modules[CS46XX_DSP_MODULES];
1707  #else /* for compatibility */
1708  	struct snd_cs46xx_pcm *playback_pcm;
1709  	unsigned int play_ctl;
1710  
1711  	struct ba1_struct *ba1;
1712  #endif
1713  
1714  #ifdef CONFIG_PM_SLEEP
1715  	u32 *saved_regs;
1716  #endif
1717  };
1718  
1719  int snd_cs46xx_create(struct snd_card *card,
1720  		      struct pci_dev *pci,
1721  		      int external_amp, int thinkpad,
1722  		      struct snd_cs46xx **rcodec);
1723  extern const struct dev_pm_ops snd_cs46xx_pm;
1724  
1725  int snd_cs46xx_pcm(struct snd_cs46xx *chip, int device);
1726  int snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device);
1727  int snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device);
1728  int snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device);
1729  int snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device);
1730  int snd_cs46xx_midi(struct snd_cs46xx *chip, int device);
1731  int snd_cs46xx_start_dsp(struct snd_cs46xx *chip);
1732  int snd_cs46xx_gameport(struct snd_cs46xx *chip);
1733  
1734  #endif /* __SOUND_CS46XX_H */
1735