| /virt/kvm/arm/vgic/ |
| D | trace.h | 11 TP_PROTO(unsigned long vcpu_id, __u32 irq, bool level),
12 TP_ARGS(vcpu_id, irq, level),
17 __field( bool, level )
23 __entry->level = level;
27 __entry->vcpu_id, __entry->irq, __entry->level)
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| D | vgic-irqfd.c | 20 int level, bool line_status) in vgic_irqfd_set_irq() argument
26 return kvm_vgic_inject_irq(kvm, 0, spi_id, level, NULL); in vgic_irqfd_set_irq()
87 int level, bool line_status) in kvm_set_msi() argument
94 if (!level) in kvm_set_msi()
107 struct kvm *kvm, int irq_source_id, int level, in kvm_arch_set_irq_inatomic() argument
110 if (e->type == KVM_IRQ_ROUTING_MSI && vgic_has_its(kvm) && level) { in kvm_arch_set_irq_inatomic()
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| D | vgic.c | 311 static bool vgic_validate_injection(struct vgic_irq *irq, bool level, void *owner) in vgic_validate_injection() argument
318 return irq->line_level != level; in vgic_validate_injection()
320 return level; in vgic_validate_injection()
438 bool level, void *owner) in kvm_vgic_inject_irq() argument
445 trace_vgic_update_irq_pending(cpuid, intid, level); in kvm_vgic_inject_irq()
461 if (!vgic_validate_injection(irq, level, owner)) { in kvm_vgic_inject_irq()
469 irq->line_level = level; in kvm_vgic_inject_irq()
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| D | vgic.h | 31 #define VGIC_AFFINITY_LEVEL(reg, level) \ argument
32 ((((reg) & VGIC_AFFINITY_## level ##_MASK) \
33 >> VGIC_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
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| D | vgic-mmio-v3.c | 886 #define SGI_AFFINITY_LEVEL(reg, level) \ argument
887 ((((reg) & ICC_SGI1R_AFFINITY_## level ##_MASK) \
888 >> ICC_SGI1R_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
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| /virt/kvm/arm/ |
| D | trace.h | 93 TP_PROTO(unsigned int type, int vcpu_idx, int irq_num, int level),
94 TP_ARGS(type, vcpu_idx, irq_num, level),
100 __field( int, level )
107 __entry->level = level;
114 __entry->type, __entry->vcpu_idx, __entry->irq_num, __entry->level)
247 TP_PROTO(unsigned long vcpu_id, __u32 irq, int level),
248 TP_ARGS(vcpu_id, irq, level),
253 __field( int, level )
259 __entry->level = level;
263 __entry->vcpu_id, __entry->irq, __entry->level)
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| D | arch_timer.c | 34 .level = 1,
39 .level = 1,
299 timer_ctx->irq.level = new_level; in kvm_timer_update_irq()
301 timer_ctx->irq.level); in kvm_timer_update_irq()
306 timer_ctx->irq.level, in kvm_timer_update_irq()
319 if (should_fire != ctx->irq.level) { in timer_emulate()
490 phys_active |= ctx->irq.level; in kvm_timer_vcpu_load_gic()
517 if (vtimer->irq.level) in kvm_timer_vcpu_load_nogic()
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| D | arm.c | 875 static int vcpu_interrupt_line(struct kvm_vcpu *vcpu, int number, bool level) in vcpu_interrupt_line() argument
887 if (level) in vcpu_interrupt_line()
895 if (set == level) in vcpu_interrupt_line()
916 bool level = irq_level->level; in kvm_vm_ioctl_irq_line() local
923 trace_kvm_irq_line(irq_type, vcpu_idx, irq_num, irq_level->level); in kvm_vm_ioctl_irq_line()
940 return vcpu_interrupt_line(vcpu, irq_num, level); in kvm_vm_ioctl_irq_line()
955 return kvm_vgic_inject_irq(kvm, vcpu->vcpu_id, irq_num, level, NULL); in kvm_vm_ioctl_irq_line()
963 return kvm_vgic_inject_irq(kvm, 0, irq_num, level, NULL); in kvm_vm_ioctl_irq_line()
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| D | psci.c | 24 #define AFFINITY_MASK(level) ~((0x1UL << ((level) * MPIDR_LEVEL_BITS)) - 1) argument
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| /virt/kvm/ |
| D | irqchip.c | 71 int kvm_set_irq(struct kvm *kvm, int irq_source_id, u32 irq, int level, in kvm_set_irq() argument
77 trace_kvm_set_irq(irq, level, irq_source_id); in kvm_set_irq()
89 r = irq_set[i].set(&irq_set[i], kvm, irq_source_id, level, in kvm_set_irq()
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| D | eventfd.c | 175 int level, in kvm_arch_set_irq_inatomic() argument
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