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Searched refs:KSEG1 (Results 1 – 14 of 14) sorted by relevance

/arch/mips/include/asm/txx9/
Djmr3927.h33 #define JMR3927_PORT_BASE KSEG1
36 #define JMR3927_ROM0_BASE (KSEG1 + JMR3927_ROMCE0)
37 #define JMR3927_ROM1_BASE (KSEG1 + JMR3927_ROMCE1)
38 #define JMR3927_IOC_BASE (KSEG1 + JMR3927_ROMCE2)
39 #define JMR3927_PCIMEM_BASE (KSEG1 + JMR3927_PCIMEM)
40 #define JMR3927_PCIIO_BASE (KSEG1 + JMR3927_PCIIO)
/arch/mips/include/asm/mach-lantiq/falcon/
Dlantiq_soc.h34 #define FALCON_CHIPID ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c))
35 #define FALCON_CHIPTYPE ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x38))
36 #define FALCON_CHIPCONF ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40))
/arch/mips/lantiq/falcon/
Dreset.c25 #define BOOT_REG_BASE (KSEG1 | 0x1F200000)
31 #define WDT_REG_BASE (KSEG1 | 0x1F8803F0)
Dprom.c34 #define BOOT_REG_BASE (KSEG1 | 0x1F200000)
/arch/mips/include/asm/
Daddrspace.h81 #define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)
89 #define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)
99 #define KSEG1 0xa0000000 macro
/arch/mips/pnx833x/common/
Dsetup.c41 set_io_port_base(KSEG1); in plat_mem_setup()
/arch/mips/rb532/
Dsetup.c50 set_io_port_base(KSEG1); in plat_mem_setup()
/arch/mips/lantiq/
Dprom.c72 set_io_port_base((unsigned long) KSEG1); in plat_mem_setup()
/arch/mips/include/asm/mach-lantiq/xway/
Dlantiq_soc.h94 #define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
/arch/mips/ralink/
Dof.c71 set_io_port_base(KSEG1); in plat_mem_setup()
/arch/mips/lasat/
Dprom.c110 set_io_port_base(KSEG1); in prom_init()
/arch/mips/ath79/
Dsetup.c220 set_io_port_base(KSEG1); in plat_mem_setup()
/arch/mips/txx9/rbtx4927/
Dsetup.c224 set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET); in rbtx4927_mem_setup()
/arch/mips/
DKconfig1136 # KSEG1 and the implementation specific "uncached accelerated" used