Searched refs:priv1 (Results 1 – 7 of 7) sorted by relevance
/arch/powerpc/platforms/cell/ |
D | spu_priv1_mmio.c | 31 old_mask = in_be64(&spu->priv1->int_mask_RW[class]); in int_mask_and() 32 out_be64(&spu->priv1->int_mask_RW[class], old_mask & mask); in int_mask_and() 39 old_mask = in_be64(&spu->priv1->int_mask_RW[class]); in int_mask_or() 40 out_be64(&spu->priv1->int_mask_RW[class], old_mask | mask); in int_mask_or() 45 out_be64(&spu->priv1->int_mask_RW[class], mask); in int_mask_set() 50 return in_be64(&spu->priv1->int_mask_RW[class]); in int_mask_get() 55 out_be64(&spu->priv1->int_stat_RW[class], stat); in int_stat_clear() 60 return in_be64(&spu->priv1->int_stat_RW[class]); in int_stat_get() 78 out_be64(&spu->priv1->int_route_RW, route); in cpu_affinity_set() 83 return in_be64(&spu->priv1->mfc_dar_RW); in mfc_dar_get() [all …]
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D | Makefile | 18 spu-priv1-$(CONFIG_PPC_CELL_COMMON) += spu_priv1_mmio.o 24 $(spu-priv1-y) \
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D | spu_manage.c | 61 iounmap(spu->priv1); in spu_unmap() 155 spu->priv1 = spu_map_prop_old(spu, node, "priv1"); in spu_map_device_old() 156 if (!spu->priv1) in spu_map_device_old() 240 (void __iomem**)&spu->priv1, NULL); in spu_map_device() 252 pr_debug(" priv1 : 0x%p\n", spu->priv1); in spu_map_device() 332 spu->local_store, spu->problem, spu->priv1, in of_create_spu()
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/arch/powerpc/platforms/cell/spufs/ |
D | backing_ops.c | 95 ctx->csa.priv1.int_stat_class2_RW &= in spu_backing_mbox_stat_poll() 97 ctx->csa.priv1.int_mask_class2_RW |= in spu_backing_mbox_stat_poll() 105 ctx->csa.priv1.int_stat_class2_RW &= in spu_backing_mbox_stat_poll() 107 ctx->csa.priv1.int_mask_class2_RW |= in spu_backing_mbox_stat_poll() 132 ctx->csa.priv1.int_mask_class2_RW |= CLASS2_ENABLE_MAILBOX_INTR; in spu_backing_ibox_read() 162 ctx->csa.priv1.int_mask_class2_RW |= in spu_backing_wbox_write() 301 sr1 = csa->priv1.mfc_sr1_RW | MFC_STATE1_MASTER_RUN_CONTROL_MASK; in spu_backing_master_start() 302 csa->priv1.mfc_sr1_RW = sr1; in spu_backing_master_start() 312 sr1 = csa->priv1.mfc_sr1_RW & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK; in spu_backing_master_stop() 313 csa->priv1.mfc_sr1_RW = sr1; in spu_backing_master_stop()
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D | switch.c | 112 csa->priv1.int_mask_class0_RW = spu_int_mask_get(spu, 0); in disable_interrupts() 113 csa->priv1.int_mask_class1_RW = spu_int_mask_get(spu, 1); in disable_interrupts() 114 csa->priv1.int_mask_class2_RW = spu_int_mask_get(spu, 2); in disable_interrupts() 217 csa->priv1.mfc_sr1_RW = spu_mfc_sr1_get(spu); in save_mfc_sr1() 442 csa->priv1.mfc_tclass_id_RW = spu_mfc_tclass_id_get(spu); in save_mfc_tclass_id() 579 csa->priv1.resource_allocation_groupID_RW = in save_mfc_rag() 581 csa->priv1.resource_allocation_enable_RW = in save_mfc_rag() 1233 csa->priv1.resource_allocation_groupID_RW); in restore_mfc_rag() 1235 csa->priv1.resource_allocation_enable_RW); in restore_mfc_rag() 1512 spu_mfc_tclass_id_set(spu, csa->priv1.mfc_tclass_id_RW); in restore_mfc_tclass_id() [all …]
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/arch/powerpc/include/asm/ |
D | spu_csa.h | 232 struct spu_priv1_collapsed priv1; member
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D | spu.h | 153 struct spu_priv1 __iomem *priv1; member
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