| /arch/m68k/coldfire/ |
| D | nettel.c | 109 writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT); in nettel_smc91x_setmac()
110 writew(macp[0], ioaddr + SMC91xx_BASEMAC); in nettel_smc91x_setmac()
111 writew(macp[1], ioaddr + SMC91xx_BASEMAC + 2); in nettel_smc91x_setmac()
112 writew(macp[2], ioaddr + SMC91xx_BASEMAC + 4); in nettel_smc91x_setmac()
125 writew(0x00ec, MCFSIM_PADDR); in nettel_smc91x_init()
127 writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT); in nettel_smc91x_init()
128 writew(0x0067, NETTEL_SMC0_ADDR + SMC91xx_BASEADDR); in nettel_smc91x_init()
132 writew(0x1180, MCFSIM_CSCR3); in nettel_smc91x_init()
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| D | m527x.c | 72 writew(par, MCFGPIO_PAR_TIMER); in m527x_qspi_init()
75 writew(0x003e, MCFGPIO_PAR_QSPI); in m527x_qspi_init()
100 writew(par, MCFGPIO_PAR_FECI2C); in m527x_i2c_init()
116 writew(sepmask, MCFGPIO_PAR_UART); in m527x_uarts_init()
133 writew(par | 0xf00, MCFGPIO_PAR_FECI2C); in m527x_fec_init()
139 writew(par | 0xa0, MCFGPIO_PAR_FECI2C); in m527x_fec_init()
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| D | m53xx.c | 169 writew(0x01f0, MCFGPIO_PAR_QSPI); in m53xx_qspi_init()
191 writew(readw(MCFGPIO_PAR_UART) | 0x0FFF, MCFGPIO_PAR_UART); in m53xx_uarts_init()
308 writew(0, MCF_WTM_WCR); in wtm_init()
344 writew(0xffff, 0x10080000); in fbcs_init()
458 writew(MCF_GPIO_PAR_UART_PAR_URXD0 | MCF_GPIO_PAR_UART_PAR_UTXD0, in gpio_init()
560 writew(MCF_CCM_CDR_LPDIV(div) | MCF_CCM_CDR_SSIDIV(temp), MCF_CCM_CDR); in clock_limp()
562 writew(readw(MCF_CCM_MISCCR) | MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR); in clock_limp()
572 writew(readw(MCF_CCM_MISCCR) & ~MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR); in clock_exit_limp()
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| D | m528x.c | 79 writew(paspar, MCFGPIO_PASPAR); in m528x_i2c_init()
103 writew(v16 | 0xf00, MCFGPIO_PASPAR); in m528x_fec_init()
123 writew(readw(MCFGPIO_PEPAR) & ~(1 << (5 * 2)), MCFGPIO_PEPAR); in wildfiremod_halt()
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| D | m520x.c | 131 writew(par, MCF_GPIO_PAR_UART); in m520x_qspi_init()
161 writew(par, MCF_GPIO_PAR_UART); in m520x_uarts_init()
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| D | m523x.c | 68 writew(par, MCFGPIO_PAR_TIMER); in m523x_qspi_init()
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| /arch/arm/mach-spear/ |
| D | time.c | 78 writew(CTRL_PRESCALER256, gpt_base + CR(CLKSRC)); in spear_clocksource_init()
84 writew(0xFFFF, gpt_base + LOAD(CLKSRC)); in spear_clocksource_init()
89 writew(val, gpt_base + CR(CLKSRC)); in spear_clocksource_init()
102 writew(val, gpt_base + CR(CLKEVT)); in timer_shutdown()
121 writew(val, gpt_base + CR(CLKEVT)); in spear_set_oneshot()
136 writew(period, gpt_base + LOAD(CLKEVT)); in spear_set_periodic()
141 writew(val, gpt_base + CR(CLKEVT)); in spear_set_periodic()
163 writew(val & ~CTRL_ENABLE, gpt_base + CR(CLKEVT)); in clockevent_next_event()
165 writew(cycles, gpt_base + LOAD(CLKEVT)); in clockevent_next_event()
168 writew(val, gpt_base + CR(CLKEVT)); in clockevent_next_event()
[all …]
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| /arch/m68k/include/asm/ |
| D | io_no.h | 81 #define writew writew macro
82 static inline void writew(u16 value, volatile void __iomem *addr) in writew() function
105 #define writew __raw_writew macro
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| D | vga.h | 27 #undef writew
34 #define writew raw_outw macro
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| D | ide.h | 46 #undef writew
53 #define writew(val, port) out_be16(port, val) macro
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| D | nettel.h | 96 writew((readw(MCFSIM_PBDAT) & ~mask) | bits, MCFSIM_PBDAT); in mcf_setppdata()
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| D | amigayle.h | 67 #define gayle_outw(v,a) writew( v, GAYLE_IO+(a) )
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| /arch/mips/include/asm/mach-jz4740/ |
| D | timer.h | 82 writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer)); in jz4740_timer_set_period()
87 writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer)); in jz4740_timer_set_duty()
92 writew(count, jz4740_timer_base + JZ_REG_TIMER_CNT(timer)); in jz4740_timer_set_count()
118 writew(ctrl, jz4740_timer_base + JZ_REG_TIMER_CTRL(timer)); in jz4740_timer_set_ctrl()
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| /arch/csky/include/asm/ |
| D | io.h | 28 #define writew(v,c) ({ wmb(); writew_relaxed((v),(c)); }) macro
32 #define writew(v,c) ({ wmb(); writew_relaxed((v),(c)); mb(); }) macro
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| /arch/sparc/include/asm/ |
| D | io_64.h | 165 #define writew writew macro
166 #define writew_relaxed writew
167 static inline void writew(u16 w, volatile void __iomem *addr) in writew() function
222 writew(w, (volatile void __iomem *)addr); in outw()
424 #define iowrite16 writew
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| /arch/parisc/include/asm/ |
| D | io.h | 201 static inline void writew(unsigned short w, volatile void __iomem *addr) in writew() function
219 #define writew writew macro
228 #define writew_relaxed(w, addr) writew(w, addr)
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| /arch/hexagon/include/asm/ |
| D | io.h | 133 static inline void writew(u16 data, volatile void __iomem *addr) in writew() function
155 #define __raw_writew writew
239 writew(data, _IO_BASE + (port & IO_SPACE_LIMIT)); in outw()
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| /arch/alpha/include/asm/ |
| D | io.h | 166 REMAP2(u16, writew, volatile) in REMAP1()
252 extern void writew(u16 b, volatile void __iomem *addr);
419 IO_CONCAT(__IO_PREFIX,writew)(b, addr); in __raw_writew()
446 extern inline void writew(u16 b, volatile void __iomem *addr) in writew() function
551 #define writew_relaxed writew
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| D | io_trivial.h | 68 IO_CONCAT(__IO_PREFIX,writew)(u16 b, volatile void __iomem *a) in IO_CONCAT() argument
95 IO_CONCAT(__IO_PREFIX,writew)(u16 b, volatile void __iomem *a) in IO_CONCAT() argument
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| /arch/nios2/include/asm/ |
| D | io.h | 25 #define writew_relaxed(x, addr) writew(x, addr)
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| /arch/x86/include/asm/ |
| D | io.h | 66 build_mmio_write(writew, "w", unsigned short, "r", :"memory")
84 #define writew writew macro
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| /arch/x86/kernel/ |
| D | early_printk.c | 42 writew(readw(VGABASE+2*(max_xpos*k+i)), in early_vga_write()
47 writew(0x720, VGABASE + 2*(max_xpos*j + i)); in early_vga_write()
62 writew(((0x7 << 8) | (unsigned short) c), in early_vga_write()
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| /arch/nios2/boot/compressed/ |
| D | console.c | 91 writew(baudclk, uartbase + ALTERA_UART_DIVISOR_REG); in console_init()
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| /arch/mips/vr41xx/common/ |
| D | pmu.c | 35 #define pmu_write(offset, value) writew((value), pmu_base + (offset))
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| /arch/nds32/include/asm/ |
| D | io.h | 80 #define writew(v,c) ({ __iowmb(); writew_relaxed((v),(c)); }) macro
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