1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Copyright 2015 Freescale Semiconductor, Inc. 4// Copyright 2016 Toradex AG 5 6#include <dt-bindings/clock/imx7d-clock.h> 7#include <dt-bindings/power/imx7-power.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/reset/imx7-reset.h> 12#include "imx7d-pinfunc.h" 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 /* 18 * The decompressor and also some bootloaders rely on a 19 * pre-existing /chosen node to be available to insert the 20 * command line and merge other ATAGS info. 21 */ 22 chosen {}; 23 24 aliases { 25 gpio0 = &gpio1; 26 gpio1 = &gpio2; 27 gpio2 = &gpio3; 28 gpio3 = &gpio4; 29 gpio4 = &gpio5; 30 gpio5 = &gpio6; 31 gpio6 = &gpio7; 32 i2c0 = &i2c1; 33 i2c1 = &i2c2; 34 i2c2 = &i2c3; 35 i2c3 = &i2c4; 36 mmc0 = &usdhc1; 37 mmc1 = &usdhc2; 38 mmc2 = &usdhc3; 39 serial0 = &uart1; 40 serial1 = &uart2; 41 serial2 = &uart3; 42 serial3 = &uart4; 43 serial4 = &uart5; 44 serial5 = &uart6; 45 serial6 = &uart7; 46 spi0 = &ecspi1; 47 spi1 = &ecspi2; 48 spi2 = &ecspi3; 49 spi3 = &ecspi4; 50 usb0 = &usbotg1; 51 usb1 = &usbh; 52 }; 53 54 cpus { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 idle-states { 59 entry-method = "psci"; 60 61 cpu_sleep_wait: cpu-sleep-wait { 62 compatible = "arm,idle-state"; 63 arm,psci-suspend-param = <0x0010000>; 64 local-timer-stop; 65 entry-latency-us = <100>; 66 exit-latency-us = <50>; 67 min-residency-us = <1000>; 68 }; 69 }; 70 71 cpu0: cpu@0 { 72 compatible = "arm,cortex-a7"; 73 device_type = "cpu"; 74 reg = <0>; 75 clock-frequency = <792000000>; 76 clock-latency = <61036>; /* two CLK32 periods */ 77 clocks = <&clks IMX7D_CLK_ARM>; 78 cpu-idle-states = <&cpu_sleep_wait>; 79 }; 80 }; 81 82 ckil: clock-cki { 83 compatible = "fixed-clock"; 84 #clock-cells = <0>; 85 clock-frequency = <32768>; 86 clock-output-names = "ckil"; 87 }; 88 89 osc: clock-osc { 90 compatible = "fixed-clock"; 91 #clock-cells = <0>; 92 clock-frequency = <24000000>; 93 clock-output-names = "osc"; 94 }; 95 96 usbphynop1: usbphynop1 { 97 compatible = "usb-nop-xceiv"; 98 clocks = <&clks IMX7D_USB_PHY1_CLK>; 99 clock-names = "main_clk"; 100 #phy-cells = <0>; 101 }; 102 103 usbphynop3: usbphynop3 { 104 compatible = "usb-nop-xceiv"; 105 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; 106 clock-names = "main_clk"; 107 #phy-cells = <0>; 108 }; 109 110 pmu { 111 compatible = "arm,cortex-a7-pmu"; 112 interrupt-parent = <&gpc>; 113 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 114 interrupt-affinity = <&cpu0>; 115 }; 116 117 replicator { 118 /* 119 * non-configurable replicators don't show up on the 120 * AMBA bus. As such no need to add "arm,primecell" 121 */ 122 compatible = "arm,coresight-static-replicator"; 123 124 out-ports { 125 #address-cells = <1>; 126 #size-cells = <0>; 127 /* replicator output ports */ 128 port@0 { 129 reg = <0>; 130 replicator_out_port0: endpoint { 131 remote-endpoint = <&tpiu_in_port>; 132 }; 133 }; 134 135 port@1 { 136 reg = <1>; 137 replicator_out_port1: endpoint { 138 remote-endpoint = <&etr_in_port>; 139 }; 140 }; 141 }; 142 143 in-ports { 144 port { 145 replicator_in_port0: endpoint { 146 remote-endpoint = <&etf_out_port>; 147 }; 148 }; 149 }; 150 }; 151 152 tempmon: tempmon { 153 compatible = "fsl,imx7d-tempmon"; 154 interrupt-parent = <&gpc>; 155 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 156 fsl,tempmon = <&anatop>; 157 nvmem-cells = <&tempmon_calib>, 158 <&tempmon_temp_grade>; 159 nvmem-cell-names = "calib", "temp_grade"; 160 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; 161 }; 162 163 timer { 164 compatible = "arm,armv7-timer"; 165 interrupt-parent = <&intc>; 166 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 167 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 168 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 169 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 170 }; 171 172 soc { 173 #address-cells = <1>; 174 #size-cells = <1>; 175 compatible = "simple-bus"; 176 interrupt-parent = <&gpc>; 177 ranges; 178 179 funnel@30041000 { 180 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 181 reg = <0x30041000 0x1000>; 182 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 183 clock-names = "apb_pclk"; 184 185 ca_funnel_in_ports: in-ports { 186 #address-cells = <1>; 187 #size-cells = <0>; 188 189 port@0 { 190 reg = <0>; 191 ca_funnel_in_port0: endpoint { 192 remote-endpoint = <&etm0_out_port>; 193 }; 194 }; 195 196 /* the other input ports are not connect to anything */ 197 }; 198 199 out-ports { 200 port { 201 ca_funnel_out_port0: endpoint { 202 remote-endpoint = <&hugo_funnel_in_port0>; 203 }; 204 }; 205 206 }; 207 }; 208 209 etm@3007c000 { 210 compatible = "arm,coresight-etm3x", "arm,primecell"; 211 reg = <0x3007c000 0x1000>; 212 cpu = <&cpu0>; 213 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 214 clock-names = "apb_pclk"; 215 216 out-ports { 217 port { 218 etm0_out_port: endpoint { 219 remote-endpoint = <&ca_funnel_in_port0>; 220 }; 221 }; 222 }; 223 }; 224 225 funnel@30083000 { 226 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 227 reg = <0x30083000 0x1000>; 228 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 229 clock-names = "apb_pclk"; 230 231 in-ports { 232 #address-cells = <1>; 233 #size-cells = <0>; 234 235 port@0 { 236 reg = <0>; 237 hugo_funnel_in_port0: endpoint { 238 remote-endpoint = <&ca_funnel_out_port0>; 239 }; 240 }; 241 242 port@1 { 243 reg = <1>; 244 hugo_funnel_in_port1: endpoint { 245 /* M4 input */ 246 }; 247 }; 248 /* the other input ports are not connect to anything */ 249 }; 250 251 out-ports { 252 port { 253 hugo_funnel_out_port0: endpoint { 254 remote-endpoint = <&etf_in_port>; 255 }; 256 }; 257 }; 258 }; 259 260 etf@30084000 { 261 compatible = "arm,coresight-tmc", "arm,primecell"; 262 reg = <0x30084000 0x1000>; 263 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 264 clock-names = "apb_pclk"; 265 266 in-ports { 267 port { 268 etf_in_port: endpoint { 269 remote-endpoint = <&hugo_funnel_out_port0>; 270 }; 271 }; 272 }; 273 274 out-ports { 275 port { 276 etf_out_port: endpoint { 277 remote-endpoint = <&replicator_in_port0>; 278 }; 279 }; 280 }; 281 }; 282 283 etr@30086000 { 284 compatible = "arm,coresight-tmc", "arm,primecell"; 285 reg = <0x30086000 0x1000>; 286 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 287 clock-names = "apb_pclk"; 288 289 in-ports { 290 port { 291 etr_in_port: endpoint { 292 remote-endpoint = <&replicator_out_port1>; 293 }; 294 }; 295 }; 296 }; 297 298 tpiu@30087000 { 299 compatible = "arm,coresight-tpiu", "arm,primecell"; 300 reg = <0x30087000 0x1000>; 301 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 302 clock-names = "apb_pclk"; 303 304 in-ports { 305 port { 306 tpiu_in_port: endpoint { 307 remote-endpoint = <&replicator_out_port0>; 308 }; 309 }; 310 }; 311 }; 312 313 intc: interrupt-controller@31001000 { 314 compatible = "arm,cortex-a7-gic"; 315 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 316 #interrupt-cells = <3>; 317 interrupt-controller; 318 interrupt-parent = <&intc>; 319 reg = <0x31001000 0x1000>, 320 <0x31002000 0x2000>, 321 <0x31004000 0x2000>, 322 <0x31006000 0x2000>; 323 }; 324 325 aips1: aips-bus@30000000 { 326 compatible = "fsl,aips-bus", "simple-bus"; 327 #address-cells = <1>; 328 #size-cells = <1>; 329 reg = <0x30000000 0x400000>; 330 ranges; 331 332 gpio1: gpio@30200000 { 333 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 334 reg = <0x30200000 0x10000>; 335 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */ 336 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */ 337 gpio-controller; 338 #gpio-cells = <2>; 339 interrupt-controller; 340 #interrupt-cells = <2>; 341 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>; 342 }; 343 344 gpio2: gpio@30210000 { 345 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 346 reg = <0x30210000 0x10000>; 347 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 348 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 349 gpio-controller; 350 #gpio-cells = <2>; 351 interrupt-controller; 352 #interrupt-cells = <2>; 353 gpio-ranges = <&iomuxc 0 13 32>; 354 }; 355 356 gpio3: gpio@30220000 { 357 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 358 reg = <0x30220000 0x10000>; 359 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 361 gpio-controller; 362 #gpio-cells = <2>; 363 interrupt-controller; 364 #interrupt-cells = <2>; 365 gpio-ranges = <&iomuxc 0 45 29>; 366 }; 367 368 gpio4: gpio@30230000 { 369 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 370 reg = <0x30230000 0x10000>; 371 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 373 gpio-controller; 374 #gpio-cells = <2>; 375 interrupt-controller; 376 #interrupt-cells = <2>; 377 gpio-ranges = <&iomuxc 0 74 24>; 378 }; 379 380 gpio5: gpio@30240000 { 381 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 382 reg = <0x30240000 0x10000>; 383 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 385 gpio-controller; 386 #gpio-cells = <2>; 387 interrupt-controller; 388 #interrupt-cells = <2>; 389 gpio-ranges = <&iomuxc 0 98 18>; 390 }; 391 392 gpio6: gpio@30250000 { 393 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 394 reg = <0x30250000 0x10000>; 395 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 396 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 397 gpio-controller; 398 #gpio-cells = <2>; 399 interrupt-controller; 400 #interrupt-cells = <2>; 401 gpio-ranges = <&iomuxc 0 116 23>; 402 }; 403 404 gpio7: gpio@30260000 { 405 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 406 reg = <0x30260000 0x10000>; 407 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 409 gpio-controller; 410 #gpio-cells = <2>; 411 interrupt-controller; 412 #interrupt-cells = <2>; 413 gpio-ranges = <&iomuxc 0 139 16>; 414 }; 415 416 wdog1: wdog@30280000 { 417 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 418 reg = <0x30280000 0x10000>; 419 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>; 421 }; 422 423 wdog2: wdog@30290000 { 424 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 425 reg = <0x30290000 0x10000>; 426 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 427 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>; 428 status = "disabled"; 429 }; 430 431 wdog3: wdog@302a0000 { 432 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 433 reg = <0x302a0000 0x10000>; 434 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 435 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>; 436 status = "disabled"; 437 }; 438 439 wdog4: wdog@302b0000 { 440 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 441 reg = <0x302b0000 0x10000>; 442 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>; 444 status = "disabled"; 445 }; 446 447 iomuxc_lpsr: iomuxc-lpsr@302c0000 { 448 compatible = "fsl,imx7d-iomuxc-lpsr"; 449 reg = <0x302c0000 0x10000>; 450 fsl,input-sel = <&iomuxc>; 451 }; 452 453 gpt1: timer@302d0000 { 454 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt"; 455 reg = <0x302d0000 0x10000>; 456 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 457 clocks = <&clks IMX7D_GPT1_ROOT_CLK>, 458 <&clks IMX7D_GPT1_ROOT_CLK>; 459 clock-names = "ipg", "per"; 460 }; 461 462 gpt2: timer@302e0000 { 463 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt"; 464 reg = <0x302e0000 0x10000>; 465 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 466 clocks = <&clks IMX7D_GPT2_ROOT_CLK>, 467 <&clks IMX7D_GPT2_ROOT_CLK>; 468 clock-names = "ipg", "per"; 469 status = "disabled"; 470 }; 471 472 gpt3: timer@302f0000 { 473 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt"; 474 reg = <0x302f0000 0x10000>; 475 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 476 clocks = <&clks IMX7D_GPT3_ROOT_CLK>, 477 <&clks IMX7D_GPT3_ROOT_CLK>; 478 clock-names = "ipg", "per"; 479 status = "disabled"; 480 }; 481 482 gpt4: timer@30300000 { 483 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt"; 484 reg = <0x30300000 0x10000>; 485 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 486 clocks = <&clks IMX7D_GPT4_ROOT_CLK>, 487 <&clks IMX7D_GPT4_ROOT_CLK>; 488 clock-names = "ipg", "per"; 489 status = "disabled"; 490 }; 491 492 kpp: kpp@30320000 { 493 compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp"; 494 reg = <0x30320000 0x10000>; 495 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 496 clocks = <&clks IMX7D_KPP_ROOT_CLK>; 497 status = "disabled"; 498 }; 499 500 iomuxc: iomuxc@30330000 { 501 compatible = "fsl,imx7d-iomuxc"; 502 reg = <0x30330000 0x10000>; 503 }; 504 505 gpr: iomuxc-gpr@30340000 { 506 compatible = "fsl,imx7d-iomuxc-gpr", 507 "fsl,imx6q-iomuxc-gpr", "syscon", 508 "simple-mfd"; 509 reg = <0x30340000 0x10000>; 510 511 mux: mux-controller { 512 compatible = "mmio-mux"; 513 #mux-control-cells = <1>; 514 mux-reg-masks = <0x14 0x00000010>; 515 }; 516 517 video_mux: csi-mux { 518 compatible = "video-mux"; 519 mux-controls = <&mux 0>; 520 #address-cells = <1>; 521 #size-cells = <0>; 522 status = "disabled"; 523 524 port@0 { 525 reg = <0>; 526 }; 527 528 port@1 { 529 reg = <1>; 530 531 csi_mux_from_mipi_vc0: endpoint { 532 remote-endpoint = <&mipi_vc0_to_csi_mux>; 533 }; 534 }; 535 536 port@2 { 537 reg = <2>; 538 539 csi_mux_to_csi: endpoint { 540 remote-endpoint = <&csi_from_csi_mux>; 541 }; 542 }; 543 }; 544 }; 545 546 ocotp: ocotp-ctrl@30350000 { 547 #address-cells = <1>; 548 #size-cells = <1>; 549 compatible = "fsl,imx7d-ocotp", "syscon"; 550 reg = <0x30350000 0x10000>; 551 clocks = <&clks IMX7D_OCOTP_CLK>; 552 553 tempmon_calib: calib@3c { 554 reg = <0x3c 0x4>; 555 }; 556 557 tempmon_temp_grade: temp-grade@10 { 558 reg = <0x10 0x4>; 559 }; 560 561 cpu_speed_grade: speed-grade@10 { 562 reg = <0x10 0x4>; 563 }; 564 }; 565 566 anatop: anatop@30360000 { 567 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop", 568 "syscon", "simple-bus"; 569 reg = <0x30360000 0x10000>; 570 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 572 573 reg_1p0d: regulator-vdd1p0d { 574 compatible = "fsl,anatop-regulator"; 575 regulator-name = "vdd1p0d"; 576 regulator-min-microvolt = <800000>; 577 regulator-max-microvolt = <1200000>; 578 anatop-reg-offset = <0x210>; 579 anatop-vol-bit-shift = <8>; 580 anatop-vol-bit-width = <5>; 581 anatop-min-bit-val = <8>; 582 anatop-min-voltage = <800000>; 583 anatop-max-voltage = <1200000>; 584 anatop-enable-bit = <0>; 585 }; 586 587 reg_1p2: regulator-vdd1p2 { 588 compatible = "fsl,anatop-regulator"; 589 regulator-name = "vdd1p2"; 590 regulator-min-microvolt = <1100000>; 591 regulator-max-microvolt = <1300000>; 592 anatop-reg-offset = <0x220>; 593 anatop-vol-bit-shift = <8>; 594 anatop-vol-bit-width = <5>; 595 anatop-min-bit-val = <0x14>; 596 anatop-min-voltage = <1100000>; 597 anatop-max-voltage = <1300000>; 598 anatop-enable-bit = <0>; 599 }; 600 }; 601 602 snvs: snvs@30370000 { 603 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 604 reg = <0x30370000 0x10000>; 605 606 snvs_rtc: snvs-rtc-lp { 607 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 608 regmap = <&snvs>; 609 offset = <0x34>; 610 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&clks IMX7D_SNVS_CLK>; 613 clock-names = "snvs-rtc"; 614 }; 615 616 snvs_pwrkey: snvs-powerkey { 617 compatible = "fsl,sec-v4.0-pwrkey"; 618 regmap = <&snvs>; 619 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 620 linux,keycode = <KEY_POWER>; 621 wakeup-source; 622 status = "disabled"; 623 }; 624 }; 625 626 clks: ccm@30380000 { 627 compatible = "fsl,imx7d-ccm"; 628 reg = <0x30380000 0x10000>; 629 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 631 #clock-cells = <1>; 632 clocks = <&ckil>, <&osc>; 633 clock-names = "ckil", "osc"; 634 }; 635 636 src: src@30390000 { 637 compatible = "fsl,imx7d-src", "syscon"; 638 reg = <0x30390000 0x10000>; 639 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 640 #reset-cells = <1>; 641 }; 642 643 gpc: gpc@303a0000 { 644 compatible = "fsl,imx7d-gpc"; 645 reg = <0x303a0000 0x10000>; 646 interrupt-controller; 647 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 648 #interrupt-cells = <3>; 649 interrupt-parent = <&intc>; 650 #power-domain-cells = <1>; 651 652 pgc { 653 #address-cells = <1>; 654 #size-cells = <0>; 655 656 pgc_mipi_phy: power-domain@0 { 657 #power-domain-cells = <0>; 658 reg = <0>; 659 power-supply = <®_1p0d>; 660 }; 661 662 pgc_pcie_phy: power-domain@1 { 663 #power-domain-cells = <0>; 664 reg = <1>; 665 power-supply = <®_1p0d>; 666 }; 667 }; 668 }; 669 }; 670 671 aips2: aips-bus@30400000 { 672 compatible = "fsl,aips-bus", "simple-bus"; 673 #address-cells = <1>; 674 #size-cells = <1>; 675 reg = <0x30400000 0x400000>; 676 ranges; 677 678 adc1: adc@30610000 { 679 compatible = "fsl,imx7d-adc"; 680 reg = <0x30610000 0x10000>; 681 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 682 clocks = <&clks IMX7D_ADC_ROOT_CLK>; 683 clock-names = "adc"; 684 #io-channel-cells = <1>; 685 status = "disabled"; 686 }; 687 688 adc2: adc@30620000 { 689 compatible = "fsl,imx7d-adc"; 690 reg = <0x30620000 0x10000>; 691 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 692 clocks = <&clks IMX7D_ADC_ROOT_CLK>; 693 clock-names = "adc"; 694 #io-channel-cells = <1>; 695 status = "disabled"; 696 }; 697 698 ecspi4: spi@30630000 { 699 #address-cells = <1>; 700 #size-cells = <0>; 701 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 702 reg = <0x30630000 0x10000>; 703 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 704 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>, 705 <&clks IMX7D_ECSPI4_ROOT_CLK>; 706 clock-names = "ipg", "per"; 707 status = "disabled"; 708 }; 709 710 pwm1: pwm@30660000 { 711 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 712 reg = <0x30660000 0x10000>; 713 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&clks IMX7D_PWM1_ROOT_CLK>, 715 <&clks IMX7D_PWM1_ROOT_CLK>; 716 clock-names = "ipg", "per"; 717 #pwm-cells = <3>; 718 status = "disabled"; 719 }; 720 721 pwm2: pwm@30670000 { 722 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 723 reg = <0x30670000 0x10000>; 724 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 725 clocks = <&clks IMX7D_PWM2_ROOT_CLK>, 726 <&clks IMX7D_PWM2_ROOT_CLK>; 727 clock-names = "ipg", "per"; 728 #pwm-cells = <3>; 729 status = "disabled"; 730 }; 731 732 pwm3: pwm@30680000 { 733 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 734 reg = <0x30680000 0x10000>; 735 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 736 clocks = <&clks IMX7D_PWM3_ROOT_CLK>, 737 <&clks IMX7D_PWM3_ROOT_CLK>; 738 clock-names = "ipg", "per"; 739 #pwm-cells = <3>; 740 status = "disabled"; 741 }; 742 743 pwm4: pwm@30690000 { 744 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 745 reg = <0x30690000 0x10000>; 746 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 747 clocks = <&clks IMX7D_PWM4_ROOT_CLK>, 748 <&clks IMX7D_PWM4_ROOT_CLK>; 749 clock-names = "ipg", "per"; 750 #pwm-cells = <3>; 751 status = "disabled"; 752 }; 753 754 csi: csi@30710000 { 755 compatible = "fsl,imx7-csi"; 756 reg = <0x30710000 0x10000>; 757 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 758 clocks = <&clks IMX7D_CLK_DUMMY>, 759 <&clks IMX7D_CSI_MCLK_ROOT_CLK>, 760 <&clks IMX7D_CLK_DUMMY>; 761 clock-names = "axi", "mclk", "dcic"; 762 status = "disabled"; 763 764 port { 765 csi_from_csi_mux: endpoint { 766 remote-endpoint = <&csi_mux_to_csi>; 767 }; 768 }; 769 }; 770 771 lcdif: lcdif@30730000 { 772 compatible = "fsl,imx7d-lcdif", "fsl,imx6sx-lcdif"; 773 reg = <0x30730000 0x10000>; 774 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 775 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, 776 <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>; 777 clock-names = "pix", "axi"; 778 status = "disabled"; 779 }; 780 781 mipi_csi: mipi-csi@30750000 { 782 compatible = "fsl,imx7-mipi-csi2"; 783 reg = <0x30750000 0x10000>; 784 #address-cells = <1>; 785 #size-cells = <0>; 786 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 787 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 788 <&clks IMX7D_MIPI_CSI_ROOT_CLK>, 789 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; 790 clock-names = "pclk", "wrap", "phy"; 791 power-domains = <&pgc_mipi_phy>; 792 phy-supply = <®_1p0d>; 793 resets = <&src IMX7_RESET_MIPI_PHY_MRST>; 794 reset-names = "mrst"; 795 status = "disabled"; 796 797 port@0 { 798 reg = <0>; 799 }; 800 801 port@1 { 802 reg = <1>; 803 804 mipi_vc0_to_csi_mux: endpoint { 805 remote-endpoint = <&csi_mux_from_mipi_vc0>; 806 }; 807 }; 808 }; 809 }; 810 811 aips3: aips-bus@30800000 { 812 compatible = "fsl,aips-bus", "simple-bus"; 813 #address-cells = <1>; 814 #size-cells = <1>; 815 reg = <0x30800000 0x400000>; 816 ranges; 817 818 spba-bus@30800000 { 819 compatible = "fsl,spba-bus", "simple-bus"; 820 #address-cells = <1>; 821 #size-cells = <1>; 822 reg = <0x30800000 0x100000>; 823 ranges; 824 825 ecspi1: spi@30820000 { 826 #address-cells = <1>; 827 #size-cells = <0>; 828 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 829 reg = <0x30820000 0x10000>; 830 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 831 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, 832 <&clks IMX7D_ECSPI1_ROOT_CLK>; 833 clock-names = "ipg", "per"; 834 status = "disabled"; 835 }; 836 837 ecspi2: spi@30830000 { 838 #address-cells = <1>; 839 #size-cells = <0>; 840 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 841 reg = <0x30830000 0x10000>; 842 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 843 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, 844 <&clks IMX7D_ECSPI2_ROOT_CLK>; 845 clock-names = "ipg", "per"; 846 status = "disabled"; 847 }; 848 849 ecspi3: spi@30840000 { 850 #address-cells = <1>; 851 #size-cells = <0>; 852 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 853 reg = <0x30840000 0x10000>; 854 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 855 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, 856 <&clks IMX7D_ECSPI3_ROOT_CLK>; 857 clock-names = "ipg", "per"; 858 status = "disabled"; 859 }; 860 861 uart1: serial@30860000 { 862 compatible = "fsl,imx7d-uart", 863 "fsl,imx6q-uart"; 864 reg = <0x30860000 0x10000>; 865 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 866 clocks = <&clks IMX7D_UART1_ROOT_CLK>, 867 <&clks IMX7D_UART1_ROOT_CLK>; 868 clock-names = "ipg", "per"; 869 status = "disabled"; 870 }; 871 872 uart2: serial@30890000 { 873 compatible = "fsl,imx7d-uart", 874 "fsl,imx6q-uart"; 875 reg = <0x30890000 0x10000>; 876 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 877 clocks = <&clks IMX7D_UART2_ROOT_CLK>, 878 <&clks IMX7D_UART2_ROOT_CLK>; 879 clock-names = "ipg", "per"; 880 status = "disabled"; 881 }; 882 883 uart3: serial@30880000 { 884 compatible = "fsl,imx7d-uart", 885 "fsl,imx6q-uart"; 886 reg = <0x30880000 0x10000>; 887 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 888 clocks = <&clks IMX7D_UART3_ROOT_CLK>, 889 <&clks IMX7D_UART3_ROOT_CLK>; 890 clock-names = "ipg", "per"; 891 status = "disabled"; 892 }; 893 894 sai1: sai@308a0000 { 895 #sound-dai-cells = <0>; 896 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 897 reg = <0x308a0000 0x10000>; 898 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 899 clocks = <&clks IMX7D_SAI1_IPG_CLK>, 900 <&clks IMX7D_SAI1_ROOT_CLK>, 901 <&clks IMX7D_CLK_DUMMY>, 902 <&clks IMX7D_CLK_DUMMY>; 903 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 904 dma-names = "rx", "tx"; 905 dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; 906 status = "disabled"; 907 }; 908 909 sai2: sai@308b0000 { 910 #sound-dai-cells = <0>; 911 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 912 reg = <0x308b0000 0x10000>; 913 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 914 clocks = <&clks IMX7D_SAI2_IPG_CLK>, 915 <&clks IMX7D_SAI2_ROOT_CLK>, 916 <&clks IMX7D_CLK_DUMMY>, 917 <&clks IMX7D_CLK_DUMMY>; 918 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 919 dma-names = "rx", "tx"; 920 dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; 921 status = "disabled"; 922 }; 923 924 sai3: sai@308c0000 { 925 #sound-dai-cells = <0>; 926 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 927 reg = <0x308c0000 0x10000>; 928 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 929 clocks = <&clks IMX7D_SAI3_IPG_CLK>, 930 <&clks IMX7D_SAI3_ROOT_CLK>, 931 <&clks IMX7D_CLK_DUMMY>, 932 <&clks IMX7D_CLK_DUMMY>; 933 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 934 dma-names = "rx", "tx"; 935 dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; 936 status = "disabled"; 937 }; 938 }; 939 940 crypto: caam@30900000 { 941 compatible = "fsl,sec-v4.0"; 942 #address-cells = <1>; 943 #size-cells = <1>; 944 reg = <0x30900000 0x40000>; 945 ranges = <0 0x30900000 0x40000>; 946 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 947 clocks = <&clks IMX7D_CAAM_CLK>, 948 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; 949 clock-names = "ipg", "aclk"; 950 951 sec_jr0: jr0@1000 { 952 compatible = "fsl,sec-v4.0-job-ring"; 953 reg = <0x1000 0x1000>; 954 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 955 }; 956 957 sec_jr1: jr1@2000 { 958 compatible = "fsl,sec-v4.0-job-ring"; 959 reg = <0x2000 0x1000>; 960 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 961 }; 962 963 sec_jr2: jr1@3000 { 964 compatible = "fsl,sec-v4.0-job-ring"; 965 reg = <0x3000 0x1000>; 966 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 967 }; 968 }; 969 970 flexcan1: can@30a00000 { 971 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; 972 reg = <0x30a00000 0x10000>; 973 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 974 clocks = <&clks IMX7D_CLK_DUMMY>, 975 <&clks IMX7D_CAN1_ROOT_CLK>; 976 clock-names = "ipg", "per"; 977 fsl,stop-mode = <&gpr 0x10 1 0x10 17>; 978 status = "disabled"; 979 }; 980 981 flexcan2: can@30a10000 { 982 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; 983 reg = <0x30a10000 0x10000>; 984 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 985 clocks = <&clks IMX7D_CLK_DUMMY>, 986 <&clks IMX7D_CAN2_ROOT_CLK>; 987 clock-names = "ipg", "per"; 988 fsl,stop-mode = <&gpr 0x10 2 0x10 18>; 989 status = "disabled"; 990 }; 991 992 i2c1: i2c@30a20000 { 993 #address-cells = <1>; 994 #size-cells = <0>; 995 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 996 reg = <0x30a20000 0x10000>; 997 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 998 clocks = <&clks IMX7D_I2C1_ROOT_CLK>; 999 status = "disabled"; 1000 }; 1001 1002 i2c2: i2c@30a30000 { 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1006 reg = <0x30a30000 0x10000>; 1007 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1008 clocks = <&clks IMX7D_I2C2_ROOT_CLK>; 1009 status = "disabled"; 1010 }; 1011 1012 i2c3: i2c@30a40000 { 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1016 reg = <0x30a40000 0x10000>; 1017 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1018 clocks = <&clks IMX7D_I2C3_ROOT_CLK>; 1019 status = "disabled"; 1020 }; 1021 1022 i2c4: i2c@30a50000 { 1023 #address-cells = <1>; 1024 #size-cells = <0>; 1025 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1026 reg = <0x30a50000 0x10000>; 1027 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1028 clocks = <&clks IMX7D_I2C4_ROOT_CLK>; 1029 status = "disabled"; 1030 }; 1031 1032 uart4: serial@30a60000 { 1033 compatible = "fsl,imx7d-uart", 1034 "fsl,imx6q-uart"; 1035 reg = <0x30a60000 0x10000>; 1036 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1037 clocks = <&clks IMX7D_UART4_ROOT_CLK>, 1038 <&clks IMX7D_UART4_ROOT_CLK>; 1039 clock-names = "ipg", "per"; 1040 status = "disabled"; 1041 }; 1042 1043 uart5: serial@30a70000 { 1044 compatible = "fsl,imx7d-uart", 1045 "fsl,imx6q-uart"; 1046 reg = <0x30a70000 0x10000>; 1047 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1048 clocks = <&clks IMX7D_UART5_ROOT_CLK>, 1049 <&clks IMX7D_UART5_ROOT_CLK>; 1050 clock-names = "ipg", "per"; 1051 status = "disabled"; 1052 }; 1053 1054 uart6: serial@30a80000 { 1055 compatible = "fsl,imx7d-uart", 1056 "fsl,imx6q-uart"; 1057 reg = <0x30a80000 0x10000>; 1058 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1059 clocks = <&clks IMX7D_UART6_ROOT_CLK>, 1060 <&clks IMX7D_UART6_ROOT_CLK>; 1061 clock-names = "ipg", "per"; 1062 status = "disabled"; 1063 }; 1064 1065 uart7: serial@30a90000 { 1066 compatible = "fsl,imx7d-uart", 1067 "fsl,imx6q-uart"; 1068 reg = <0x30a90000 0x10000>; 1069 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1070 clocks = <&clks IMX7D_UART7_ROOT_CLK>, 1071 <&clks IMX7D_UART7_ROOT_CLK>; 1072 clock-names = "ipg", "per"; 1073 status = "disabled"; 1074 }; 1075 1076 mu0a: mailbox@30aa0000 { 1077 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; 1078 reg = <0x30aa0000 0x10000>; 1079 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1080 clocks = <&clks IMX7D_MU_ROOT_CLK>; 1081 #mbox-cells = <2>; 1082 status = "disabled"; 1083 }; 1084 1085 mu0b: mailbox@30ab0000 { 1086 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; 1087 reg = <0x30ab0000 0x10000>; 1088 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1089 clocks = <&clks IMX7D_MU_ROOT_CLK>; 1090 #mbox-cells = <2>; 1091 fsl,mu-side-b; 1092 status = "disabled"; 1093 }; 1094 1095 usbotg1: usb@30b10000 { 1096 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 1097 reg = <0x30b10000 0x200>; 1098 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1099 clocks = <&clks IMX7D_USB_CTRL_CLK>; 1100 fsl,usbphy = <&usbphynop1>; 1101 fsl,usbmisc = <&usbmisc1 0>; 1102 phy-clkgate-delay-us = <400>; 1103 status = "disabled"; 1104 }; 1105 1106 usbh: usb@30b30000 { 1107 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 1108 reg = <0x30b30000 0x200>; 1109 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1110 clocks = <&clks IMX7D_USB_CTRL_CLK>; 1111 fsl,usbphy = <&usbphynop3>; 1112 fsl,usbmisc = <&usbmisc3 0>; 1113 phy_type = "hsic"; 1114 dr_mode = "host"; 1115 phy-clkgate-delay-us = <400>; 1116 status = "disabled"; 1117 }; 1118 1119 usbmisc1: usbmisc@30b10200 { 1120 #index-cells = <1>; 1121 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 1122 reg = <0x30b10200 0x200>; 1123 }; 1124 1125 usbmisc3: usbmisc@30b30200 { 1126 #index-cells = <1>; 1127 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 1128 reg = <0x30b30200 0x200>; 1129 }; 1130 1131 usdhc1: usdhc@30b40000 { 1132 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1133 reg = <0x30b40000 0x10000>; 1134 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1135 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1136 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1137 <&clks IMX7D_USDHC1_ROOT_CLK>; 1138 clock-names = "ipg", "ahb", "per"; 1139 bus-width = <4>; 1140 fsl,tuning-step = <2>; 1141 fsl,tuning-start-tap = <20>; 1142 status = "disabled"; 1143 }; 1144 1145 usdhc2: usdhc@30b50000 { 1146 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1147 reg = <0x30b50000 0x10000>; 1148 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1149 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1150 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1151 <&clks IMX7D_USDHC2_ROOT_CLK>; 1152 clock-names = "ipg", "ahb", "per"; 1153 bus-width = <4>; 1154 fsl,tuning-step = <2>; 1155 fsl,tuning-start-tap = <20>; 1156 status = "disabled"; 1157 }; 1158 1159 usdhc3: usdhc@30b60000 { 1160 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1161 reg = <0x30b60000 0x10000>; 1162 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1163 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1164 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1165 <&clks IMX7D_USDHC3_ROOT_CLK>; 1166 clock-names = "ipg", "ahb", "per"; 1167 bus-width = <4>; 1168 fsl,tuning-step = <2>; 1169 fsl,tuning-start-tap = <20>; 1170 status = "disabled"; 1171 }; 1172 1173 sdma: sdma@30bd0000 { 1174 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; 1175 reg = <0x30bd0000 0x10000>; 1176 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1177 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1178 <&clks IMX7D_SDMA_CORE_CLK>; 1179 clock-names = "ipg", "ahb"; 1180 #dma-cells = <3>; 1181 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1182 }; 1183 1184 fec1: ethernet@30be0000 { 1185 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; 1186 reg = <0x30be0000 0x10000>; 1187 interrupt-names = "int0", "int1", "int2", "pps"; 1188 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1191 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1192 clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>, 1193 <&clks IMX7D_ENET_AXI_ROOT_CLK>, 1194 <&clks IMX7D_ENET1_TIME_ROOT_CLK>, 1195 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, 1196 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; 1197 clock-names = "ipg", "ahb", "ptp", 1198 "enet_clk_ref", "enet_out"; 1199 fsl,num-tx-queues = <3>; 1200 fsl,num-rx-queues = <3>; 1201 status = "disabled"; 1202 }; 1203 }; 1204 1205 dma_apbh: dma-controller@33000000 { 1206 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 1207 reg = <0x33000000 0x2000>; 1208 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1212 #dma-cells = <1>; 1213 dma-channels = <4>; 1214 clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; 1215 }; 1216 1217 gpmi: gpmi-nand@33002000{ 1218 compatible = "fsl,imx7d-gpmi-nand"; 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 1222 reg-names = "gpmi-nand", "bch"; 1223 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1224 interrupt-names = "bch"; 1225 clocks = <&clks IMX7D_NAND_RAWNAND_CLK>, 1226 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; 1227 clock-names = "gpmi_io", "gpmi_bch_apb"; 1228 dmas = <&dma_apbh 0>; 1229 dma-names = "rx-tx"; 1230 status = "disabled"; 1231 assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>; 1232 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>; 1233 }; 1234 }; 1235}; 1236