1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 4 * 5 * Based on "omap4.dtsi" 6 */ 7 8#include <dt-bindings/bus/ti-sysc.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/pinctrl/omap.h> 12#include <dt-bindings/clock/omap5.h> 13 14/ { 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 compatible = "ti,omap5"; 19 interrupt-parent = <&wakeupgen>; 20 chosen { }; 21 22 aliases { 23 i2c0 = &i2c1; 24 i2c1 = &i2c2; 25 i2c2 = &i2c3; 26 i2c3 = &i2c4; 27 i2c4 = &i2c5; 28 mmc0 = &mmc1; 29 mmc1 = &mmc2; 30 mmc2 = &mmc3; 31 mmc3 = &mmc4; 32 mmc4 = &mmc5; 33 serial0 = &uart1; 34 serial1 = &uart2; 35 serial2 = &uart3; 36 serial3 = &uart4; 37 serial4 = &uart5; 38 serial5 = &uart6; 39 }; 40 41 cpus { 42 #address-cells = <1>; 43 #size-cells = <0>; 44 45 cpu0: cpu@0 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a15"; 48 reg = <0x0>; 49 50 operating-points = < 51 /* kHz uV */ 52 1000000 1060000 53 1500000 1250000 54 >; 55 56 clocks = <&dpll_mpu_ck>; 57 clock-names = "cpu"; 58 59 clock-latency = <300000>; /* From omap-cpufreq driver */ 60 61 /* cooling options */ 62 #cooling-cells = <2>; /* min followed by max */ 63 }; 64 cpu@1 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a15"; 67 reg = <0x1>; 68 69 operating-points = < 70 /* kHz uV */ 71 1000000 1060000 72 1500000 1250000 73 >; 74 75 clocks = <&dpll_mpu_ck>; 76 clock-names = "cpu"; 77 78 clock-latency = <300000>; /* From omap-cpufreq driver */ 79 80 /* cooling options */ 81 #cooling-cells = <2>; /* min followed by max */ 82 }; 83 }; 84 85 thermal-zones { 86 #include "omap4-cpu-thermal.dtsi" 87 #include "omap5-gpu-thermal.dtsi" 88 #include "omap5-core-thermal.dtsi" 89 }; 90 91 timer { 92 compatible = "arm,armv7-timer"; 93 /* PPI secure/nonsecure IRQ */ 94 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, 95 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, 96 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, 97 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>; 98 interrupt-parent = <&gic>; 99 }; 100 101 pmu { 102 compatible = "arm,cortex-a15-pmu"; 103 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 105 }; 106 107 gic: interrupt-controller@48211000 { 108 compatible = "arm,cortex-a15-gic"; 109 interrupt-controller; 110 #interrupt-cells = <3>; 111 reg = <0 0x48211000 0 0x1000>, 112 <0 0x48212000 0 0x2000>, 113 <0 0x48214000 0 0x2000>, 114 <0 0x48216000 0 0x2000>; 115 interrupt-parent = <&gic>; 116 }; 117 118 wakeupgen: interrupt-controller@48281000 { 119 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; 120 interrupt-controller; 121 #interrupt-cells = <3>; 122 reg = <0 0x48281000 0 0x1000>; 123 interrupt-parent = <&gic>; 124 }; 125 126 /* 127 * The soc node represents the soc top level view. It is used for IPs 128 * that are not memory mapped in the MPU view or for the MPU itself. 129 */ 130 soc { 131 compatible = "ti,omap-infra"; 132 mpu { 133 compatible = "ti,omap4-mpu"; 134 ti,hwmods = "mpu"; 135 sram = <&ocmcram>; 136 }; 137 }; 138 139 /* 140 * XXX: Use a flat representation of the OMAP3 interconnect. 141 * The real OMAP interconnect network is quite complex. 142 * Since it will not bring real advantage to represent that in DT for 143 * the moment, just use a fake OCP bus entry to represent the whole bus 144 * hierarchy. 145 */ 146 ocp { 147 compatible = "ti,omap5-l3-noc", "simple-bus"; 148 #address-cells = <1>; 149 #size-cells = <1>; 150 ranges = <0 0 0 0xc0000000>; 151 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>; 152 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; 153 reg = <0 0x44000000 0 0x2000>, 154 <0 0x44800000 0 0x3000>, 155 <0 0x45000000 0 0x4000>; 156 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 158 159 l4_wkup: interconnect@4ae00000 { 160 }; 161 162 l4_cfg: interconnect@4a000000 { 163 }; 164 165 l4_per: interconnect@48000000 { 166 }; 167 168 l4_abe: interconnect@40100000 { 169 }; 170 171 ocmcram: ocmcram@40300000 { 172 compatible = "mmio-sram"; 173 reg = <0x40300000 0x20000>; /* 128k */ 174 }; 175 176 gpmc: gpmc@50000000 { 177 compatible = "ti,omap4430-gpmc"; 178 reg = <0x50000000 0x1000>; 179 #address-cells = <2>; 180 #size-cells = <1>; 181 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 182 dmas = <&sdma 4>; 183 dma-names = "rxtx"; 184 gpmc,num-cs = <8>; 185 gpmc,num-waitpins = <4>; 186 ti,hwmods = "gpmc"; 187 clocks = <&l3_iclk_div>; 188 clock-names = "fck"; 189 interrupt-controller; 190 #interrupt-cells = <2>; 191 gpio-controller; 192 #gpio-cells = <2>; 193 }; 194 195 mmu_dsp: mmu@4a066000 { 196 compatible = "ti,omap4-iommu"; 197 reg = <0x4a066000 0x100>; 198 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 199 ti,hwmods = "mmu_dsp"; 200 #iommu-cells = <0>; 201 }; 202 203 mmu_ipu: mmu@55082000 { 204 compatible = "ti,omap4-iommu"; 205 reg = <0x55082000 0x100>; 206 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 207 ti,hwmods = "mmu_ipu"; 208 #iommu-cells = <0>; 209 ti,iommu-bus-err-back; 210 }; 211 212 dmm@4e000000 { 213 compatible = "ti,omap5-dmm"; 214 reg = <0x4e000000 0x800>; 215 interrupts = <0 113 0x4>; 216 ti,hwmods = "dmm"; 217 }; 218 219 emif1: emif@4c000000 { 220 compatible = "ti,emif-4d5"; 221 ti,hwmods = "emif1"; 222 ti,no-idle-on-init; 223 phy-type = <2>; /* DDR PHY type: Intelli PHY */ 224 reg = <0x4c000000 0x400>; 225 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 226 hw-caps-read-idle-ctrl; 227 hw-caps-ll-interface; 228 hw-caps-temp-alert; 229 }; 230 231 emif2: emif@4d000000 { 232 compatible = "ti,emif-4d5"; 233 ti,hwmods = "emif2"; 234 ti,no-idle-on-init; 235 phy-type = <2>; /* DDR PHY type: Intelli PHY */ 236 reg = <0x4d000000 0x400>; 237 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 238 hw-caps-read-idle-ctrl; 239 hw-caps-ll-interface; 240 hw-caps-temp-alert; 241 }; 242 243 bandgap: bandgap@4a0021e0 { 244 reg = <0x4a0021e0 0xc 245 0x4a00232c 0xc 246 0x4a002380 0x2c 247 0x4a0023C0 0x3c>; 248 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 249 compatible = "ti,omap5430-bandgap"; 250 251 #thermal-sensor-cells = <1>; 252 }; 253 254 /* OCP2SCP3 */ 255 sata: sata@4a141100 { 256 compatible = "snps,dwc-ahci"; 257 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; 258 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 259 phys = <&sata_phy>; 260 phy-names = "sata-phy"; 261 clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; 262 ti,hwmods = "sata"; 263 ports-implemented = <0x1>; 264 }; 265 266 target-module@56000000 { 267 compatible = "ti,sysc-omap4", "ti,sysc"; 268 reg = <0x5600fe00 0x4>, 269 <0x5600fe10 0x4>; 270 reg-names = "rev", "sysc"; 271 ti,sysc-midle = <SYSC_IDLE_FORCE>, 272 <SYSC_IDLE_NO>, 273 <SYSC_IDLE_SMART>; 274 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 275 <SYSC_IDLE_NO>, 276 <SYSC_IDLE_SMART>; 277 clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>; 278 clock-names = "fck"; 279 #address-cells = <1>; 280 #size-cells = <1>; 281 ranges = <0 0x56000000 0x2000000>; 282 283 /* 284 * Closed source PowerVR driver, no child device 285 * binding or driver in mainline 286 */ 287 }; 288 289 dss: dss@58000000 { 290 compatible = "ti,omap5-dss"; 291 reg = <0x58000000 0x80>; 292 status = "disabled"; 293 ti,hwmods = "dss_core"; 294 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; 295 clock-names = "fck"; 296 #address-cells = <1>; 297 #size-cells = <1>; 298 ranges; 299 300 dispc@58001000 { 301 compatible = "ti,omap5-dispc"; 302 reg = <0x58001000 0x1000>; 303 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 304 ti,hwmods = "dss_dispc"; 305 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; 306 clock-names = "fck"; 307 }; 308 309 rfbi: encoder@58002000 { 310 compatible = "ti,omap5-rfbi"; 311 reg = <0x58002000 0x100>; 312 status = "disabled"; 313 ti,hwmods = "dss_rfbi"; 314 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>; 315 clock-names = "fck", "ick"; 316 }; 317 318 dsi1: encoder@58004000 { 319 compatible = "ti,omap5-dsi"; 320 reg = <0x58004000 0x200>, 321 <0x58004200 0x40>, 322 <0x58004300 0x40>; 323 reg-names = "proto", "phy", "pll"; 324 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 325 status = "disabled"; 326 ti,hwmods = "dss_dsi1"; 327 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, 328 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; 329 clock-names = "fck", "sys_clk"; 330 }; 331 332 dsi2: encoder@58005000 { 333 compatible = "ti,omap5-dsi"; 334 reg = <0x58009000 0x200>, 335 <0x58009200 0x40>, 336 <0x58009300 0x40>; 337 reg-names = "proto", "phy", "pll"; 338 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 339 status = "disabled"; 340 ti,hwmods = "dss_dsi2"; 341 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, 342 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; 343 clock-names = "fck", "sys_clk"; 344 }; 345 346 hdmi: encoder@58060000 { 347 compatible = "ti,omap5-hdmi"; 348 reg = <0x58040000 0x200>, 349 <0x58040200 0x80>, 350 <0x58040300 0x80>, 351 <0x58060000 0x19000>; 352 reg-names = "wp", "pll", "phy", "core"; 353 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 354 status = "disabled"; 355 ti,hwmods = "dss_hdmi"; 356 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, 357 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; 358 clock-names = "fck", "sys_clk"; 359 dmas = <&sdma 76>; 360 dma-names = "audio_tx"; 361 }; 362 }; 363 364 abb_mpu: regulator-abb-mpu { 365 compatible = "ti,abb-v2"; 366 regulator-name = "abb_mpu"; 367 #address-cells = <0>; 368 #size-cells = <0>; 369 clocks = <&sys_clkin>; 370 ti,settling-time = <50>; 371 ti,clock-cycles = <16>; 372 373 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>, 374 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>; 375 reg-names = "base-address", "int-address", 376 "efuse-address", "ldo-address"; 377 ti,tranxdone-status-mask = <0x80>; 378 /* LDOVBBMPU_MUX_CTRL */ 379 ti,ldovbb-override-mask = <0x400>; 380 /* LDOVBBMPU_VSET_OUT */ 381 ti,ldovbb-vset-mask = <0x1F>; 382 383 /* 384 * NOTE: only FBB mode used but actual vset will 385 * determine final biasing 386 */ 387 ti,abb_info = < 388 /*uV ABB efuse rbb_m fbb_m vset_m*/ 389 1060000 0 0x0 0 0x02000000 0x01F00000 390 1250000 0 0x4 0 0x02000000 0x01F00000 391 >; 392 }; 393 394 abb_mm: regulator-abb-mm { 395 compatible = "ti,abb-v2"; 396 regulator-name = "abb_mm"; 397 #address-cells = <0>; 398 #size-cells = <0>; 399 clocks = <&sys_clkin>; 400 ti,settling-time = <50>; 401 ti,clock-cycles = <16>; 402 403 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>, 404 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>; 405 reg-names = "base-address", "int-address", 406 "efuse-address", "ldo-address"; 407 ti,tranxdone-status-mask = <0x80000000>; 408 /* LDOVBBMM_MUX_CTRL */ 409 ti,ldovbb-override-mask = <0x400>; 410 /* LDOVBBMM_VSET_OUT */ 411 ti,ldovbb-vset-mask = <0x1F>; 412 413 /* 414 * NOTE: only FBB mode used but actual vset will 415 * determine final biasing 416 */ 417 ti,abb_info = < 418 /*uV ABB efuse rbb_m fbb_m vset_m*/ 419 1025000 0 0x0 0 0x02000000 0x01F00000 420 1120000 0 0x4 0 0x02000000 0x01F00000 421 >; 422 }; 423 }; 424}; 425 426&cpu_thermal { 427 polling-delay = <500>; /* milliseconds */ 428 coefficients = <65 (-1791)>; 429}; 430 431#include "omap5-l4.dtsi" 432#include "omap54xx-clocks.dtsi" 433 434&gpu_thermal { 435 coefficients = <117 (-2992)>; 436}; 437 438&core_thermal { 439 coefficients = <0 2000>; 440}; 441 442#include "omap5-l4-abe.dtsi" 443#include "omap54xx-clocks.dtsi" 444