1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * Copyright (C) 2002,2003 Intel Corp. 4 * Jun Nakajima <jun.nakajima@intel.com> 5 * Suresh Siddha <suresh.b.siddha@intel.com> 6 */ 7 8 #ifndef _ASM_IA64_IA64REGS_H 9 #define _ASM_IA64_IA64REGS_H 10 11 /* 12 * Register Names for getreg() and setreg(). 13 * 14 * The "magic" numbers happen to match the values used by the Intel compiler's 15 * getreg()/setreg() intrinsics. 16 */ 17 18 /* Special Registers */ 19 20 #define _IA64_REG_IP 1016 /* getreg only */ 21 #define _IA64_REG_PSR 1019 22 #define _IA64_REG_PSR_L 1019 23 24 /* General Integer Registers */ 25 26 #define _IA64_REG_GP 1025 /* R1 */ 27 #define _IA64_REG_R8 1032 /* R8 */ 28 #define _IA64_REG_R9 1033 /* R9 */ 29 #define _IA64_REG_SP 1036 /* R12 */ 30 #define _IA64_REG_TP 1037 /* R13 */ 31 32 /* Application Registers */ 33 34 #define _IA64_REG_AR_KR0 3072 35 #define _IA64_REG_AR_KR1 3073 36 #define _IA64_REG_AR_KR2 3074 37 #define _IA64_REG_AR_KR3 3075 38 #define _IA64_REG_AR_KR4 3076 39 #define _IA64_REG_AR_KR5 3077 40 #define _IA64_REG_AR_KR6 3078 41 #define _IA64_REG_AR_KR7 3079 42 #define _IA64_REG_AR_RSC 3088 43 #define _IA64_REG_AR_BSP 3089 44 #define _IA64_REG_AR_BSPSTORE 3090 45 #define _IA64_REG_AR_RNAT 3091 46 #define _IA64_REG_AR_FCR 3093 47 #define _IA64_REG_AR_EFLAG 3096 48 #define _IA64_REG_AR_CSD 3097 49 #define _IA64_REG_AR_SSD 3098 50 #define _IA64_REG_AR_CFLAG 3099 51 #define _IA64_REG_AR_FSR 3100 52 #define _IA64_REG_AR_FIR 3101 53 #define _IA64_REG_AR_FDR 3102 54 #define _IA64_REG_AR_CCV 3104 55 #define _IA64_REG_AR_UNAT 3108 56 #define _IA64_REG_AR_FPSR 3112 57 #define _IA64_REG_AR_ITC 3116 58 #define _IA64_REG_AR_PFS 3136 59 #define _IA64_REG_AR_LC 3137 60 #define _IA64_REG_AR_EC 3138 61 62 /* Control Registers */ 63 64 #define _IA64_REG_CR_DCR 4096 65 #define _IA64_REG_CR_ITM 4097 66 #define _IA64_REG_CR_IVA 4098 67 #define _IA64_REG_CR_PTA 4104 68 #define _IA64_REG_CR_IPSR 4112 69 #define _IA64_REG_CR_ISR 4113 70 #define _IA64_REG_CR_IIP 4115 71 #define _IA64_REG_CR_IFA 4116 72 #define _IA64_REG_CR_ITIR 4117 73 #define _IA64_REG_CR_IIPA 4118 74 #define _IA64_REG_CR_IFS 4119 75 #define _IA64_REG_CR_IIM 4120 76 #define _IA64_REG_CR_IHA 4121 77 #define _IA64_REG_CR_LID 4160 78 #define _IA64_REG_CR_IVR 4161 /* getreg only */ 79 #define _IA64_REG_CR_TPR 4162 80 #define _IA64_REG_CR_EOI 4163 81 #define _IA64_REG_CR_IRR0 4164 /* getreg only */ 82 #define _IA64_REG_CR_IRR1 4165 /* getreg only */ 83 #define _IA64_REG_CR_IRR2 4166 /* getreg only */ 84 #define _IA64_REG_CR_IRR3 4167 /* getreg only */ 85 #define _IA64_REG_CR_ITV 4168 86 #define _IA64_REG_CR_PMV 4169 87 #define _IA64_REG_CR_CMCV 4170 88 #define _IA64_REG_CR_LRR0 4176 89 #define _IA64_REG_CR_LRR1 4177 90 91 /* Indirect Registers for getindreg() and setindreg() */ 92 93 #define _IA64_REG_INDR_CPUID 9000 /* getindreg only */ 94 #define _IA64_REG_INDR_DBR 9001 95 #define _IA64_REG_INDR_IBR 9002 96 #define _IA64_REG_INDR_PKR 9003 97 #define _IA64_REG_INDR_PMC 9004 98 #define _IA64_REG_INDR_PMD 9005 99 #define _IA64_REG_INDR_RR 9006 100 101 #endif /* _ASM_IA64_IA64REGS_H */ 102