1 // SPDX-License-Identifier: GPL-2.0
2 /* Nehalem/SandBridge/Haswell/Broadwell/Skylake uncore support */
3 #include "uncore.h"
4
5 /* Uncore IMC PCI IDs */
6 #define PCI_DEVICE_ID_INTEL_SNB_IMC 0x0100
7 #define PCI_DEVICE_ID_INTEL_IVB_IMC 0x0154
8 #define PCI_DEVICE_ID_INTEL_IVB_E3_IMC 0x0150
9 #define PCI_DEVICE_ID_INTEL_HSW_IMC 0x0c00
10 #define PCI_DEVICE_ID_INTEL_HSW_U_IMC 0x0a04
11 #define PCI_DEVICE_ID_INTEL_BDW_IMC 0x1604
12 #define PCI_DEVICE_ID_INTEL_SKL_U_IMC 0x1904
13 #define PCI_DEVICE_ID_INTEL_SKL_Y_IMC 0x190c
14 #define PCI_DEVICE_ID_INTEL_SKL_HD_IMC 0x1900
15 #define PCI_DEVICE_ID_INTEL_SKL_HQ_IMC 0x1910
16 #define PCI_DEVICE_ID_INTEL_SKL_SD_IMC 0x190f
17 #define PCI_DEVICE_ID_INTEL_SKL_SQ_IMC 0x191f
18 #define PCI_DEVICE_ID_INTEL_SKL_E3_IMC 0x1918
19 #define PCI_DEVICE_ID_INTEL_KBL_Y_IMC 0x590c
20 #define PCI_DEVICE_ID_INTEL_KBL_U_IMC 0x5904
21 #define PCI_DEVICE_ID_INTEL_KBL_UQ_IMC 0x5914
22 #define PCI_DEVICE_ID_INTEL_KBL_SD_IMC 0x590f
23 #define PCI_DEVICE_ID_INTEL_KBL_SQ_IMC 0x591f
24 #define PCI_DEVICE_ID_INTEL_KBL_HQ_IMC 0x5910
25 #define PCI_DEVICE_ID_INTEL_KBL_WQ_IMC 0x5918
26 #define PCI_DEVICE_ID_INTEL_CFL_2U_IMC 0x3ecc
27 #define PCI_DEVICE_ID_INTEL_CFL_4U_IMC 0x3ed0
28 #define PCI_DEVICE_ID_INTEL_CFL_4H_IMC 0x3e10
29 #define PCI_DEVICE_ID_INTEL_CFL_6H_IMC 0x3ec4
30 #define PCI_DEVICE_ID_INTEL_CFL_2S_D_IMC 0x3e0f
31 #define PCI_DEVICE_ID_INTEL_CFL_4S_D_IMC 0x3e1f
32 #define PCI_DEVICE_ID_INTEL_CFL_6S_D_IMC 0x3ec2
33 #define PCI_DEVICE_ID_INTEL_CFL_8S_D_IMC 0x3e30
34 #define PCI_DEVICE_ID_INTEL_CFL_4S_W_IMC 0x3e18
35 #define PCI_DEVICE_ID_INTEL_CFL_6S_W_IMC 0x3ec6
36 #define PCI_DEVICE_ID_INTEL_CFL_8S_W_IMC 0x3e31
37 #define PCI_DEVICE_ID_INTEL_CFL_4S_S_IMC 0x3e33
38 #define PCI_DEVICE_ID_INTEL_CFL_6S_S_IMC 0x3eca
39 #define PCI_DEVICE_ID_INTEL_CFL_8S_S_IMC 0x3e32
40 #define PCI_DEVICE_ID_INTEL_AML_YD_IMC 0x590c
41 #define PCI_DEVICE_ID_INTEL_AML_YQ_IMC 0x590d
42 #define PCI_DEVICE_ID_INTEL_WHL_UQ_IMC 0x3ed0
43 #define PCI_DEVICE_ID_INTEL_WHL_4_UQ_IMC 0x3e34
44 #define PCI_DEVICE_ID_INTEL_WHL_UD_IMC 0x3e35
45 #define PCI_DEVICE_ID_INTEL_ICL_U_IMC 0x8a02
46 #define PCI_DEVICE_ID_INTEL_ICL_U2_IMC 0x8a12
47
48
49 /* SNB event control */
50 #define SNB_UNC_CTL_EV_SEL_MASK 0x000000ff
51 #define SNB_UNC_CTL_UMASK_MASK 0x0000ff00
52 #define SNB_UNC_CTL_EDGE_DET (1 << 18)
53 #define SNB_UNC_CTL_EN (1 << 22)
54 #define SNB_UNC_CTL_INVERT (1 << 23)
55 #define SNB_UNC_CTL_CMASK_MASK 0x1f000000
56 #define NHM_UNC_CTL_CMASK_MASK 0xff000000
57 #define NHM_UNC_FIXED_CTR_CTL_EN (1 << 0)
58
59 #define SNB_UNC_RAW_EVENT_MASK (SNB_UNC_CTL_EV_SEL_MASK | \
60 SNB_UNC_CTL_UMASK_MASK | \
61 SNB_UNC_CTL_EDGE_DET | \
62 SNB_UNC_CTL_INVERT | \
63 SNB_UNC_CTL_CMASK_MASK)
64
65 #define NHM_UNC_RAW_EVENT_MASK (SNB_UNC_CTL_EV_SEL_MASK | \
66 SNB_UNC_CTL_UMASK_MASK | \
67 SNB_UNC_CTL_EDGE_DET | \
68 SNB_UNC_CTL_INVERT | \
69 NHM_UNC_CTL_CMASK_MASK)
70
71 /* SNB global control register */
72 #define SNB_UNC_PERF_GLOBAL_CTL 0x391
73 #define SNB_UNC_FIXED_CTR_CTRL 0x394
74 #define SNB_UNC_FIXED_CTR 0x395
75
76 /* SNB uncore global control */
77 #define SNB_UNC_GLOBAL_CTL_CORE_ALL ((1 << 4) - 1)
78 #define SNB_UNC_GLOBAL_CTL_EN (1 << 29)
79
80 /* SNB Cbo register */
81 #define SNB_UNC_CBO_0_PERFEVTSEL0 0x700
82 #define SNB_UNC_CBO_0_PER_CTR0 0x706
83 #define SNB_UNC_CBO_MSR_OFFSET 0x10
84
85 /* SNB ARB register */
86 #define SNB_UNC_ARB_PER_CTR0 0x3b0
87 #define SNB_UNC_ARB_PERFEVTSEL0 0x3b2
88 #define SNB_UNC_ARB_MSR_OFFSET 0x10
89
90 /* NHM global control register */
91 #define NHM_UNC_PERF_GLOBAL_CTL 0x391
92 #define NHM_UNC_FIXED_CTR 0x394
93 #define NHM_UNC_FIXED_CTR_CTRL 0x395
94
95 /* NHM uncore global control */
96 #define NHM_UNC_GLOBAL_CTL_EN_PC_ALL ((1ULL << 8) - 1)
97 #define NHM_UNC_GLOBAL_CTL_EN_FC (1ULL << 32)
98
99 /* NHM uncore register */
100 #define NHM_UNC_PERFEVTSEL0 0x3c0
101 #define NHM_UNC_UNCORE_PMC0 0x3b0
102
103 /* SKL uncore global control */
104 #define SKL_UNC_PERF_GLOBAL_CTL 0xe01
105 #define SKL_UNC_GLOBAL_CTL_CORE_ALL ((1 << 5) - 1)
106
107 /* ICL Cbo register */
108 #define ICL_UNC_CBO_CONFIG 0x396
109 #define ICL_UNC_NUM_CBO_MASK 0xf
110 #define ICL_UNC_CBO_0_PER_CTR0 0x702
111 #define ICL_UNC_CBO_MSR_OFFSET 0x8
112
113 /* ICL ARB register */
114 #define ICL_UNC_ARB_PER_CTR 0x3b1
115 #define ICL_UNC_ARB_PERFEVTSEL 0x3b3
116
117 DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
118 DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
119 DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18");
120 DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
121 DEFINE_UNCORE_FORMAT_ATTR(cmask5, cmask, "config:24-28");
122 DEFINE_UNCORE_FORMAT_ATTR(cmask8, cmask, "config:24-31");
123
124 /* Sandy Bridge uncore support */
snb_uncore_msr_enable_event(struct intel_uncore_box * box,struct perf_event * event)125 static void snb_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
126 {
127 struct hw_perf_event *hwc = &event->hw;
128
129 if (hwc->idx < UNCORE_PMC_IDX_FIXED)
130 wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN);
131 else
132 wrmsrl(hwc->config_base, SNB_UNC_CTL_EN);
133 }
134
snb_uncore_msr_disable_event(struct intel_uncore_box * box,struct perf_event * event)135 static void snb_uncore_msr_disable_event(struct intel_uncore_box *box, struct perf_event *event)
136 {
137 wrmsrl(event->hw.config_base, 0);
138 }
139
snb_uncore_msr_init_box(struct intel_uncore_box * box)140 static void snb_uncore_msr_init_box(struct intel_uncore_box *box)
141 {
142 if (box->pmu->pmu_idx == 0) {
143 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL,
144 SNB_UNC_GLOBAL_CTL_EN | SNB_UNC_GLOBAL_CTL_CORE_ALL);
145 }
146 }
147
snb_uncore_msr_enable_box(struct intel_uncore_box * box)148 static void snb_uncore_msr_enable_box(struct intel_uncore_box *box)
149 {
150 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL,
151 SNB_UNC_GLOBAL_CTL_EN | SNB_UNC_GLOBAL_CTL_CORE_ALL);
152 }
153
snb_uncore_msr_exit_box(struct intel_uncore_box * box)154 static void snb_uncore_msr_exit_box(struct intel_uncore_box *box)
155 {
156 if (box->pmu->pmu_idx == 0)
157 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, 0);
158 }
159
160 static struct uncore_event_desc snb_uncore_events[] = {
161 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x00"),
162 { /* end: all zeroes */ },
163 };
164
165 static struct attribute *snb_uncore_formats_attr[] = {
166 &format_attr_event.attr,
167 &format_attr_umask.attr,
168 &format_attr_edge.attr,
169 &format_attr_inv.attr,
170 &format_attr_cmask5.attr,
171 NULL,
172 };
173
174 static const struct attribute_group snb_uncore_format_group = {
175 .name = "format",
176 .attrs = snb_uncore_formats_attr,
177 };
178
179 static struct intel_uncore_ops snb_uncore_msr_ops = {
180 .init_box = snb_uncore_msr_init_box,
181 .enable_box = snb_uncore_msr_enable_box,
182 .exit_box = snb_uncore_msr_exit_box,
183 .disable_event = snb_uncore_msr_disable_event,
184 .enable_event = snb_uncore_msr_enable_event,
185 .read_counter = uncore_msr_read_counter,
186 };
187
188 static struct event_constraint snb_uncore_arb_constraints[] = {
189 UNCORE_EVENT_CONSTRAINT(0x80, 0x1),
190 UNCORE_EVENT_CONSTRAINT(0x83, 0x1),
191 EVENT_CONSTRAINT_END
192 };
193
194 static struct intel_uncore_type snb_uncore_cbox = {
195 .name = "cbox",
196 .num_counters = 2,
197 .num_boxes = 4,
198 .perf_ctr_bits = 44,
199 .fixed_ctr_bits = 48,
200 .perf_ctr = SNB_UNC_CBO_0_PER_CTR0,
201 .event_ctl = SNB_UNC_CBO_0_PERFEVTSEL0,
202 .fixed_ctr = SNB_UNC_FIXED_CTR,
203 .fixed_ctl = SNB_UNC_FIXED_CTR_CTRL,
204 .single_fixed = 1,
205 .event_mask = SNB_UNC_RAW_EVENT_MASK,
206 .msr_offset = SNB_UNC_CBO_MSR_OFFSET,
207 .ops = &snb_uncore_msr_ops,
208 .format_group = &snb_uncore_format_group,
209 .event_descs = snb_uncore_events,
210 };
211
212 static struct intel_uncore_type snb_uncore_arb = {
213 .name = "arb",
214 .num_counters = 2,
215 .num_boxes = 1,
216 .perf_ctr_bits = 44,
217 .perf_ctr = SNB_UNC_ARB_PER_CTR0,
218 .event_ctl = SNB_UNC_ARB_PERFEVTSEL0,
219 .event_mask = SNB_UNC_RAW_EVENT_MASK,
220 .msr_offset = SNB_UNC_ARB_MSR_OFFSET,
221 .constraints = snb_uncore_arb_constraints,
222 .ops = &snb_uncore_msr_ops,
223 .format_group = &snb_uncore_format_group,
224 };
225
226 static struct intel_uncore_type *snb_msr_uncores[] = {
227 &snb_uncore_cbox,
228 &snb_uncore_arb,
229 NULL,
230 };
231
snb_uncore_cpu_init(void)232 void snb_uncore_cpu_init(void)
233 {
234 uncore_msr_uncores = snb_msr_uncores;
235 if (snb_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores)
236 snb_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores;
237 }
238
skl_uncore_msr_init_box(struct intel_uncore_box * box)239 static void skl_uncore_msr_init_box(struct intel_uncore_box *box)
240 {
241 if (box->pmu->pmu_idx == 0) {
242 wrmsrl(SKL_UNC_PERF_GLOBAL_CTL,
243 SNB_UNC_GLOBAL_CTL_EN | SKL_UNC_GLOBAL_CTL_CORE_ALL);
244 }
245
246 /* The 8th CBOX has different MSR space */
247 if (box->pmu->pmu_idx == 7)
248 __set_bit(UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS, &box->flags);
249 }
250
skl_uncore_msr_enable_box(struct intel_uncore_box * box)251 static void skl_uncore_msr_enable_box(struct intel_uncore_box *box)
252 {
253 wrmsrl(SKL_UNC_PERF_GLOBAL_CTL,
254 SNB_UNC_GLOBAL_CTL_EN | SKL_UNC_GLOBAL_CTL_CORE_ALL);
255 }
256
skl_uncore_msr_exit_box(struct intel_uncore_box * box)257 static void skl_uncore_msr_exit_box(struct intel_uncore_box *box)
258 {
259 if (box->pmu->pmu_idx == 0)
260 wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, 0);
261 }
262
263 static struct intel_uncore_ops skl_uncore_msr_ops = {
264 .init_box = skl_uncore_msr_init_box,
265 .enable_box = skl_uncore_msr_enable_box,
266 .exit_box = skl_uncore_msr_exit_box,
267 .disable_event = snb_uncore_msr_disable_event,
268 .enable_event = snb_uncore_msr_enable_event,
269 .read_counter = uncore_msr_read_counter,
270 };
271
272 static struct intel_uncore_type skl_uncore_cbox = {
273 .name = "cbox",
274 .num_counters = 4,
275 .num_boxes = 8,
276 .perf_ctr_bits = 44,
277 .fixed_ctr_bits = 48,
278 .perf_ctr = SNB_UNC_CBO_0_PER_CTR0,
279 .event_ctl = SNB_UNC_CBO_0_PERFEVTSEL0,
280 .fixed_ctr = SNB_UNC_FIXED_CTR,
281 .fixed_ctl = SNB_UNC_FIXED_CTR_CTRL,
282 .single_fixed = 1,
283 .event_mask = SNB_UNC_RAW_EVENT_MASK,
284 .msr_offset = SNB_UNC_CBO_MSR_OFFSET,
285 .ops = &skl_uncore_msr_ops,
286 .format_group = &snb_uncore_format_group,
287 .event_descs = snb_uncore_events,
288 };
289
290 static struct intel_uncore_type *skl_msr_uncores[] = {
291 &skl_uncore_cbox,
292 &snb_uncore_arb,
293 NULL,
294 };
295
skl_uncore_cpu_init(void)296 void skl_uncore_cpu_init(void)
297 {
298 uncore_msr_uncores = skl_msr_uncores;
299 if (skl_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores)
300 skl_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores;
301 snb_uncore_arb.ops = &skl_uncore_msr_ops;
302 }
303
304 static struct intel_uncore_ops icl_uncore_msr_ops = {
305 .disable_event = snb_uncore_msr_disable_event,
306 .enable_event = snb_uncore_msr_enable_event,
307 .read_counter = uncore_msr_read_counter,
308 };
309
310 static struct intel_uncore_type icl_uncore_cbox = {
311 .name = "cbox",
312 .num_counters = 2,
313 .perf_ctr_bits = 44,
314 .perf_ctr = ICL_UNC_CBO_0_PER_CTR0,
315 .event_ctl = SNB_UNC_CBO_0_PERFEVTSEL0,
316 .event_mask = SNB_UNC_RAW_EVENT_MASK,
317 .msr_offset = ICL_UNC_CBO_MSR_OFFSET,
318 .ops = &icl_uncore_msr_ops,
319 .format_group = &snb_uncore_format_group,
320 };
321
322 static struct uncore_event_desc icl_uncore_events[] = {
323 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff"),
324 { /* end: all zeroes */ },
325 };
326
327 static struct attribute *icl_uncore_clock_formats_attr[] = {
328 &format_attr_event.attr,
329 NULL,
330 };
331
332 static struct attribute_group icl_uncore_clock_format_group = {
333 .name = "format",
334 .attrs = icl_uncore_clock_formats_attr,
335 };
336
337 static struct intel_uncore_type icl_uncore_clockbox = {
338 .name = "clock",
339 .num_counters = 1,
340 .num_boxes = 1,
341 .fixed_ctr_bits = 48,
342 .fixed_ctr = SNB_UNC_FIXED_CTR,
343 .fixed_ctl = SNB_UNC_FIXED_CTR_CTRL,
344 .single_fixed = 1,
345 .event_mask = SNB_UNC_CTL_EV_SEL_MASK,
346 .format_group = &icl_uncore_clock_format_group,
347 .ops = &icl_uncore_msr_ops,
348 .event_descs = icl_uncore_events,
349 };
350
351 static struct intel_uncore_type icl_uncore_arb = {
352 .name = "arb",
353 .num_counters = 1,
354 .num_boxes = 1,
355 .perf_ctr_bits = 44,
356 .perf_ctr = ICL_UNC_ARB_PER_CTR,
357 .event_ctl = ICL_UNC_ARB_PERFEVTSEL,
358 .event_mask = SNB_UNC_RAW_EVENT_MASK,
359 .ops = &icl_uncore_msr_ops,
360 .format_group = &snb_uncore_format_group,
361 };
362
363 static struct intel_uncore_type *icl_msr_uncores[] = {
364 &icl_uncore_cbox,
365 &icl_uncore_arb,
366 &icl_uncore_clockbox,
367 NULL,
368 };
369
icl_get_cbox_num(void)370 static int icl_get_cbox_num(void)
371 {
372 u64 num_boxes;
373
374 rdmsrl(ICL_UNC_CBO_CONFIG, num_boxes);
375
376 return num_boxes & ICL_UNC_NUM_CBO_MASK;
377 }
378
icl_uncore_cpu_init(void)379 void icl_uncore_cpu_init(void)
380 {
381 uncore_msr_uncores = icl_msr_uncores;
382 icl_uncore_cbox.num_boxes = icl_get_cbox_num();
383 }
384
385 enum {
386 SNB_PCI_UNCORE_IMC,
387 };
388
389 static struct uncore_event_desc snb_uncore_imc_events[] = {
390 INTEL_UNCORE_EVENT_DESC(data_reads, "event=0x01"),
391 INTEL_UNCORE_EVENT_DESC(data_reads.scale, "6.103515625e-5"),
392 INTEL_UNCORE_EVENT_DESC(data_reads.unit, "MiB"),
393
394 INTEL_UNCORE_EVENT_DESC(data_writes, "event=0x02"),
395 INTEL_UNCORE_EVENT_DESC(data_writes.scale, "6.103515625e-5"),
396 INTEL_UNCORE_EVENT_DESC(data_writes.unit, "MiB"),
397
398 { /* end: all zeroes */ },
399 };
400
401 #define SNB_UNCORE_PCI_IMC_EVENT_MASK 0xff
402 #define SNB_UNCORE_PCI_IMC_BAR_OFFSET 0x48
403
404 /* page size multiple covering all config regs */
405 #define SNB_UNCORE_PCI_IMC_MAP_SIZE 0x6000
406
407 #define SNB_UNCORE_PCI_IMC_DATA_READS 0x1
408 #define SNB_UNCORE_PCI_IMC_DATA_READS_BASE 0x5050
409 #define SNB_UNCORE_PCI_IMC_DATA_WRITES 0x2
410 #define SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE 0x5054
411 #define SNB_UNCORE_PCI_IMC_CTR_BASE SNB_UNCORE_PCI_IMC_DATA_READS_BASE
412
413 enum perf_snb_uncore_imc_freerunning_types {
414 SNB_PCI_UNCORE_IMC_DATA = 0,
415 SNB_PCI_UNCORE_IMC_FREERUNNING_TYPE_MAX,
416 };
417
418 static struct freerunning_counters snb_uncore_imc_freerunning[] = {
419 [SNB_PCI_UNCORE_IMC_DATA] = { SNB_UNCORE_PCI_IMC_DATA_READS_BASE, 0x4, 0x0, 2, 32 },
420 };
421
422 static struct attribute *snb_uncore_imc_formats_attr[] = {
423 &format_attr_event.attr,
424 NULL,
425 };
426
427 static const struct attribute_group snb_uncore_imc_format_group = {
428 .name = "format",
429 .attrs = snb_uncore_imc_formats_attr,
430 };
431
snb_uncore_imc_init_box(struct intel_uncore_box * box)432 static void snb_uncore_imc_init_box(struct intel_uncore_box *box)
433 {
434 struct pci_dev *pdev = box->pci_dev;
435 int where = SNB_UNCORE_PCI_IMC_BAR_OFFSET;
436 resource_size_t addr;
437 u32 pci_dword;
438
439 pci_read_config_dword(pdev, where, &pci_dword);
440 addr = pci_dword;
441
442 #ifdef CONFIG_PHYS_ADDR_T_64BIT
443 pci_read_config_dword(pdev, where + 4, &pci_dword);
444 addr |= ((resource_size_t)pci_dword << 32);
445 #endif
446
447 addr &= ~(PAGE_SIZE - 1);
448
449 box->io_addr = ioremap(addr, SNB_UNCORE_PCI_IMC_MAP_SIZE);
450 box->hrtimer_duration = UNCORE_SNB_IMC_HRTIMER_INTERVAL;
451 }
452
snb_uncore_imc_enable_box(struct intel_uncore_box * box)453 static void snb_uncore_imc_enable_box(struct intel_uncore_box *box)
454 {}
455
snb_uncore_imc_disable_box(struct intel_uncore_box * box)456 static void snb_uncore_imc_disable_box(struct intel_uncore_box *box)
457 {}
458
snb_uncore_imc_enable_event(struct intel_uncore_box * box,struct perf_event * event)459 static void snb_uncore_imc_enable_event(struct intel_uncore_box *box, struct perf_event *event)
460 {}
461
snb_uncore_imc_disable_event(struct intel_uncore_box * box,struct perf_event * event)462 static void snb_uncore_imc_disable_event(struct intel_uncore_box *box, struct perf_event *event)
463 {}
464
465 /*
466 * Keep the custom event_init() function compatible with old event
467 * encoding for free running counters.
468 */
snb_uncore_imc_event_init(struct perf_event * event)469 static int snb_uncore_imc_event_init(struct perf_event *event)
470 {
471 struct intel_uncore_pmu *pmu;
472 struct intel_uncore_box *box;
473 struct hw_perf_event *hwc = &event->hw;
474 u64 cfg = event->attr.config & SNB_UNCORE_PCI_IMC_EVENT_MASK;
475 int idx, base;
476
477 if (event->attr.type != event->pmu->type)
478 return -ENOENT;
479
480 pmu = uncore_event_to_pmu(event);
481 /* no device found for this pmu */
482 if (pmu->func_id < 0)
483 return -ENOENT;
484
485 /* Sampling not supported yet */
486 if (hwc->sample_period)
487 return -EINVAL;
488
489 /* unsupported modes and filters */
490 if (event->attr.sample_period) /* no sampling */
491 return -EINVAL;
492
493 /*
494 * Place all uncore events for a particular physical package
495 * onto a single cpu
496 */
497 if (event->cpu < 0)
498 return -EINVAL;
499
500 /* check only supported bits are set */
501 if (event->attr.config & ~SNB_UNCORE_PCI_IMC_EVENT_MASK)
502 return -EINVAL;
503
504 box = uncore_pmu_to_box(pmu, event->cpu);
505 if (!box || box->cpu < 0)
506 return -EINVAL;
507
508 event->cpu = box->cpu;
509 event->pmu_private = box;
510
511 event->event_caps |= PERF_EV_CAP_READ_ACTIVE_PKG;
512
513 event->hw.idx = -1;
514 event->hw.last_tag = ~0ULL;
515 event->hw.extra_reg.idx = EXTRA_REG_NONE;
516 event->hw.branch_reg.idx = EXTRA_REG_NONE;
517 /*
518 * check event is known (whitelist, determines counter)
519 */
520 switch (cfg) {
521 case SNB_UNCORE_PCI_IMC_DATA_READS:
522 base = SNB_UNCORE_PCI_IMC_DATA_READS_BASE;
523 idx = UNCORE_PMC_IDX_FREERUNNING;
524 break;
525 case SNB_UNCORE_PCI_IMC_DATA_WRITES:
526 base = SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE;
527 idx = UNCORE_PMC_IDX_FREERUNNING;
528 break;
529 default:
530 return -EINVAL;
531 }
532
533 /* must be done before validate_group */
534 event->hw.event_base = base;
535 event->hw.idx = idx;
536
537 /* Convert to standard encoding format for freerunning counters */
538 event->hw.config = ((cfg - 1) << 8) | 0x10ff;
539
540 /* no group validation needed, we have free running counters */
541
542 return 0;
543 }
544
snb_uncore_imc_hw_config(struct intel_uncore_box * box,struct perf_event * event)545 static int snb_uncore_imc_hw_config(struct intel_uncore_box *box, struct perf_event *event)
546 {
547 return 0;
548 }
549
snb_pci2phy_map_init(int devid)550 int snb_pci2phy_map_init(int devid)
551 {
552 struct pci_dev *dev = NULL;
553 struct pci2phy_map *map;
554 int bus, segment;
555
556 dev = pci_get_device(PCI_VENDOR_ID_INTEL, devid, dev);
557 if (!dev)
558 return -ENOTTY;
559
560 bus = dev->bus->number;
561 segment = pci_domain_nr(dev->bus);
562
563 raw_spin_lock(&pci2phy_map_lock);
564 map = __find_pci2phy_map(segment);
565 if (!map) {
566 raw_spin_unlock(&pci2phy_map_lock);
567 pci_dev_put(dev);
568 return -ENOMEM;
569 }
570 map->pbus_to_physid[bus] = 0;
571 raw_spin_unlock(&pci2phy_map_lock);
572
573 pci_dev_put(dev);
574
575 return 0;
576 }
577
snb_uncore_imc_read_counter(struct intel_uncore_box * box,struct perf_event * event)578 static u64 snb_uncore_imc_read_counter(struct intel_uncore_box *box, struct perf_event *event)
579 {
580 struct hw_perf_event *hwc = &event->hw;
581
582 /*
583 * SNB IMC counters are 32-bit and are laid out back to back
584 * in MMIO space. Therefore we must use a 32-bit accessor function
585 * using readq() from uncore_mmio_read_counter() causes problems
586 * because it is reading 64-bit at a time. This is okay for the
587 * uncore_perf_event_update() function because it drops the upper
588 * 32-bits but not okay for plain uncore_read_counter() as invoked
589 * in uncore_pmu_event_start().
590 */
591 return (u64)readl(box->io_addr + hwc->event_base);
592 }
593
594 static struct pmu snb_uncore_imc_pmu = {
595 .task_ctx_nr = perf_invalid_context,
596 .event_init = snb_uncore_imc_event_init,
597 .add = uncore_pmu_event_add,
598 .del = uncore_pmu_event_del,
599 .start = uncore_pmu_event_start,
600 .stop = uncore_pmu_event_stop,
601 .read = uncore_pmu_event_read,
602 .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
603 };
604
605 static struct intel_uncore_ops snb_uncore_imc_ops = {
606 .init_box = snb_uncore_imc_init_box,
607 .exit_box = uncore_mmio_exit_box,
608 .enable_box = snb_uncore_imc_enable_box,
609 .disable_box = snb_uncore_imc_disable_box,
610 .disable_event = snb_uncore_imc_disable_event,
611 .enable_event = snb_uncore_imc_enable_event,
612 .hw_config = snb_uncore_imc_hw_config,
613 .read_counter = snb_uncore_imc_read_counter,
614 };
615
616 static struct intel_uncore_type snb_uncore_imc = {
617 .name = "imc",
618 .num_counters = 2,
619 .num_boxes = 1,
620 .num_freerunning_types = SNB_PCI_UNCORE_IMC_FREERUNNING_TYPE_MAX,
621 .freerunning = snb_uncore_imc_freerunning,
622 .event_descs = snb_uncore_imc_events,
623 .format_group = &snb_uncore_imc_format_group,
624 .ops = &snb_uncore_imc_ops,
625 .pmu = &snb_uncore_imc_pmu,
626 };
627
628 static struct intel_uncore_type *snb_pci_uncores[] = {
629 [SNB_PCI_UNCORE_IMC] = &snb_uncore_imc,
630 NULL,
631 };
632
633 static const struct pci_device_id snb_uncore_pci_ids[] = {
634 { /* IMC */
635 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SNB_IMC),
636 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
637 },
638 { /* end: all zeroes */ },
639 };
640
641 static const struct pci_device_id ivb_uncore_pci_ids[] = {
642 { /* IMC */
643 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_IMC),
644 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
645 },
646 { /* IMC */
647 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_E3_IMC),
648 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
649 },
650 { /* end: all zeroes */ },
651 };
652
653 static const struct pci_device_id hsw_uncore_pci_ids[] = {
654 { /* IMC */
655 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HSW_IMC),
656 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
657 },
658 { /* IMC */
659 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HSW_U_IMC),
660 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
661 },
662 { /* end: all zeroes */ },
663 };
664
665 static const struct pci_device_id bdw_uncore_pci_ids[] = {
666 { /* IMC */
667 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_IMC),
668 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
669 },
670 { /* end: all zeroes */ },
671 };
672
673 static const struct pci_device_id skl_uncore_pci_ids[] = {
674 { /* IMC */
675 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_Y_IMC),
676 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
677 },
678 { /* IMC */
679 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_U_IMC),
680 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
681 },
682 { /* IMC */
683 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_HD_IMC),
684 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
685 },
686 { /* IMC */
687 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_HQ_IMC),
688 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
689 },
690 { /* IMC */
691 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_SD_IMC),
692 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
693 },
694 { /* IMC */
695 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_SQ_IMC),
696 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
697 },
698 { /* IMC */
699 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_E3_IMC),
700 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
701 },
702 { /* IMC */
703 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_Y_IMC),
704 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
705 },
706 { /* IMC */
707 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_U_IMC),
708 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
709 },
710 { /* IMC */
711 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_UQ_IMC),
712 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
713 },
714 { /* IMC */
715 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_SD_IMC),
716 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
717 },
718 { /* IMC */
719 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_SQ_IMC),
720 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
721 },
722 { /* IMC */
723 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_HQ_IMC),
724 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
725 },
726 { /* IMC */
727 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_WQ_IMC),
728 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
729 },
730 { /* IMC */
731 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_2U_IMC),
732 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
733 },
734 { /* IMC */
735 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4U_IMC),
736 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
737 },
738 { /* IMC */
739 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4H_IMC),
740 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
741 },
742 { /* IMC */
743 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_6H_IMC),
744 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
745 },
746 { /* IMC */
747 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_2S_D_IMC),
748 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
749 },
750 { /* IMC */
751 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4S_D_IMC),
752 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
753 },
754 { /* IMC */
755 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_6S_D_IMC),
756 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
757 },
758 { /* IMC */
759 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_8S_D_IMC),
760 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
761 },
762 { /* IMC */
763 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4S_W_IMC),
764 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
765 },
766 { /* IMC */
767 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_6S_W_IMC),
768 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
769 },
770 { /* IMC */
771 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_8S_W_IMC),
772 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
773 },
774 { /* IMC */
775 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4S_S_IMC),
776 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
777 },
778 { /* IMC */
779 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_6S_S_IMC),
780 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
781 },
782 { /* IMC */
783 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_8S_S_IMC),
784 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
785 },
786 { /* IMC */
787 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AML_YD_IMC),
788 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
789 },
790 { /* IMC */
791 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AML_YQ_IMC),
792 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
793 },
794 { /* IMC */
795 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WHL_UQ_IMC),
796 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
797 },
798 { /* IMC */
799 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WHL_4_UQ_IMC),
800 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
801 },
802 { /* IMC */
803 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WHL_UD_IMC),
804 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
805 },
806 { /* end: all zeroes */ },
807 };
808
809 static const struct pci_device_id icl_uncore_pci_ids[] = {
810 { /* IMC */
811 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICL_U_IMC),
812 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
813 },
814 { /* IMC */
815 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICL_U2_IMC),
816 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
817 },
818 { /* end: all zeroes */ },
819 };
820
821 static struct pci_driver snb_uncore_pci_driver = {
822 .name = "snb_uncore",
823 .id_table = snb_uncore_pci_ids,
824 };
825
826 static struct pci_driver ivb_uncore_pci_driver = {
827 .name = "ivb_uncore",
828 .id_table = ivb_uncore_pci_ids,
829 };
830
831 static struct pci_driver hsw_uncore_pci_driver = {
832 .name = "hsw_uncore",
833 .id_table = hsw_uncore_pci_ids,
834 };
835
836 static struct pci_driver bdw_uncore_pci_driver = {
837 .name = "bdw_uncore",
838 .id_table = bdw_uncore_pci_ids,
839 };
840
841 static struct pci_driver skl_uncore_pci_driver = {
842 .name = "skl_uncore",
843 .id_table = skl_uncore_pci_ids,
844 };
845
846 static struct pci_driver icl_uncore_pci_driver = {
847 .name = "icl_uncore",
848 .id_table = icl_uncore_pci_ids,
849 };
850
851 struct imc_uncore_pci_dev {
852 __u32 pci_id;
853 struct pci_driver *driver;
854 };
855 #define IMC_DEV(a, d) \
856 { .pci_id = PCI_DEVICE_ID_INTEL_##a, .driver = (d) }
857
858 static const struct imc_uncore_pci_dev desktop_imc_pci_ids[] = {
859 IMC_DEV(SNB_IMC, &snb_uncore_pci_driver),
860 IMC_DEV(IVB_IMC, &ivb_uncore_pci_driver), /* 3rd Gen Core processor */
861 IMC_DEV(IVB_E3_IMC, &ivb_uncore_pci_driver), /* Xeon E3-1200 v2/3rd Gen Core processor */
862 IMC_DEV(HSW_IMC, &hsw_uncore_pci_driver), /* 4th Gen Core Processor */
863 IMC_DEV(HSW_U_IMC, &hsw_uncore_pci_driver), /* 4th Gen Core ULT Mobile Processor */
864 IMC_DEV(BDW_IMC, &bdw_uncore_pci_driver), /* 5th Gen Core U */
865 IMC_DEV(SKL_Y_IMC, &skl_uncore_pci_driver), /* 6th Gen Core Y */
866 IMC_DEV(SKL_U_IMC, &skl_uncore_pci_driver), /* 6th Gen Core U */
867 IMC_DEV(SKL_HD_IMC, &skl_uncore_pci_driver), /* 6th Gen Core H Dual Core */
868 IMC_DEV(SKL_HQ_IMC, &skl_uncore_pci_driver), /* 6th Gen Core H Quad Core */
869 IMC_DEV(SKL_SD_IMC, &skl_uncore_pci_driver), /* 6th Gen Core S Dual Core */
870 IMC_DEV(SKL_SQ_IMC, &skl_uncore_pci_driver), /* 6th Gen Core S Quad Core */
871 IMC_DEV(SKL_E3_IMC, &skl_uncore_pci_driver), /* Xeon E3 V5 Gen Core processor */
872 IMC_DEV(KBL_Y_IMC, &skl_uncore_pci_driver), /* 7th Gen Core Y */
873 IMC_DEV(KBL_U_IMC, &skl_uncore_pci_driver), /* 7th Gen Core U */
874 IMC_DEV(KBL_UQ_IMC, &skl_uncore_pci_driver), /* 7th Gen Core U Quad Core */
875 IMC_DEV(KBL_SD_IMC, &skl_uncore_pci_driver), /* 7th Gen Core S Dual Core */
876 IMC_DEV(KBL_SQ_IMC, &skl_uncore_pci_driver), /* 7th Gen Core S Quad Core */
877 IMC_DEV(KBL_HQ_IMC, &skl_uncore_pci_driver), /* 7th Gen Core H Quad Core */
878 IMC_DEV(KBL_WQ_IMC, &skl_uncore_pci_driver), /* 7th Gen Core S 4 cores Work Station */
879 IMC_DEV(CFL_2U_IMC, &skl_uncore_pci_driver), /* 8th Gen Core U 2 Cores */
880 IMC_DEV(CFL_4U_IMC, &skl_uncore_pci_driver), /* 8th Gen Core U 4 Cores */
881 IMC_DEV(CFL_4H_IMC, &skl_uncore_pci_driver), /* 8th Gen Core H 4 Cores */
882 IMC_DEV(CFL_6H_IMC, &skl_uncore_pci_driver), /* 8th Gen Core H 6 Cores */
883 IMC_DEV(CFL_2S_D_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 2 Cores Desktop */
884 IMC_DEV(CFL_4S_D_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 4 Cores Desktop */
885 IMC_DEV(CFL_6S_D_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 6 Cores Desktop */
886 IMC_DEV(CFL_8S_D_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 8 Cores Desktop */
887 IMC_DEV(CFL_4S_W_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 4 Cores Work Station */
888 IMC_DEV(CFL_6S_W_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 6 Cores Work Station */
889 IMC_DEV(CFL_8S_W_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 8 Cores Work Station */
890 IMC_DEV(CFL_4S_S_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 4 Cores Server */
891 IMC_DEV(CFL_6S_S_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 6 Cores Server */
892 IMC_DEV(CFL_8S_S_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 8 Cores Server */
893 IMC_DEV(AML_YD_IMC, &skl_uncore_pci_driver), /* 8th Gen Core Y Mobile Dual Core */
894 IMC_DEV(AML_YQ_IMC, &skl_uncore_pci_driver), /* 8th Gen Core Y Mobile Quad Core */
895 IMC_DEV(WHL_UQ_IMC, &skl_uncore_pci_driver), /* 8th Gen Core U Mobile Quad Core */
896 IMC_DEV(WHL_4_UQ_IMC, &skl_uncore_pci_driver), /* 8th Gen Core U Mobile Quad Core */
897 IMC_DEV(WHL_UD_IMC, &skl_uncore_pci_driver), /* 8th Gen Core U Mobile Dual Core */
898 IMC_DEV(ICL_U_IMC, &icl_uncore_pci_driver), /* 10th Gen Core Mobile */
899 IMC_DEV(ICL_U2_IMC, &icl_uncore_pci_driver), /* 10th Gen Core Mobile */
900 { /* end marker */ }
901 };
902
903
904 #define for_each_imc_pci_id(x, t) \
905 for (x = (t); (x)->pci_id; x++)
906
imc_uncore_find_dev(void)907 static struct pci_driver *imc_uncore_find_dev(void)
908 {
909 const struct imc_uncore_pci_dev *p;
910 int ret;
911
912 for_each_imc_pci_id(p, desktop_imc_pci_ids) {
913 ret = snb_pci2phy_map_init(p->pci_id);
914 if (ret == 0)
915 return p->driver;
916 }
917 return NULL;
918 }
919
imc_uncore_pci_init(void)920 static int imc_uncore_pci_init(void)
921 {
922 struct pci_driver *imc_drv = imc_uncore_find_dev();
923
924 if (!imc_drv)
925 return -ENODEV;
926
927 uncore_pci_uncores = snb_pci_uncores;
928 uncore_pci_driver = imc_drv;
929
930 return 0;
931 }
932
snb_uncore_pci_init(void)933 int snb_uncore_pci_init(void)
934 {
935 return imc_uncore_pci_init();
936 }
937
ivb_uncore_pci_init(void)938 int ivb_uncore_pci_init(void)
939 {
940 return imc_uncore_pci_init();
941 }
hsw_uncore_pci_init(void)942 int hsw_uncore_pci_init(void)
943 {
944 return imc_uncore_pci_init();
945 }
946
bdw_uncore_pci_init(void)947 int bdw_uncore_pci_init(void)
948 {
949 return imc_uncore_pci_init();
950 }
951
skl_uncore_pci_init(void)952 int skl_uncore_pci_init(void)
953 {
954 return imc_uncore_pci_init();
955 }
956
957 /* end of Sandy Bridge uncore support */
958
959 /* Nehalem uncore support */
nhm_uncore_msr_disable_box(struct intel_uncore_box * box)960 static void nhm_uncore_msr_disable_box(struct intel_uncore_box *box)
961 {
962 wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, 0);
963 }
964
nhm_uncore_msr_enable_box(struct intel_uncore_box * box)965 static void nhm_uncore_msr_enable_box(struct intel_uncore_box *box)
966 {
967 wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, NHM_UNC_GLOBAL_CTL_EN_PC_ALL | NHM_UNC_GLOBAL_CTL_EN_FC);
968 }
969
nhm_uncore_msr_enable_event(struct intel_uncore_box * box,struct perf_event * event)970 static void nhm_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
971 {
972 struct hw_perf_event *hwc = &event->hw;
973
974 if (hwc->idx < UNCORE_PMC_IDX_FIXED)
975 wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN);
976 else
977 wrmsrl(hwc->config_base, NHM_UNC_FIXED_CTR_CTL_EN);
978 }
979
980 static struct attribute *nhm_uncore_formats_attr[] = {
981 &format_attr_event.attr,
982 &format_attr_umask.attr,
983 &format_attr_edge.attr,
984 &format_attr_inv.attr,
985 &format_attr_cmask8.attr,
986 NULL,
987 };
988
989 static const struct attribute_group nhm_uncore_format_group = {
990 .name = "format",
991 .attrs = nhm_uncore_formats_attr,
992 };
993
994 static struct uncore_event_desc nhm_uncore_events[] = {
995 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x00"),
996 INTEL_UNCORE_EVENT_DESC(qmc_writes_full_any, "event=0x2f,umask=0x0f"),
997 INTEL_UNCORE_EVENT_DESC(qmc_normal_reads_any, "event=0x2c,umask=0x0f"),
998 INTEL_UNCORE_EVENT_DESC(qhl_request_ioh_reads, "event=0x20,umask=0x01"),
999 INTEL_UNCORE_EVENT_DESC(qhl_request_ioh_writes, "event=0x20,umask=0x02"),
1000 INTEL_UNCORE_EVENT_DESC(qhl_request_remote_reads, "event=0x20,umask=0x04"),
1001 INTEL_UNCORE_EVENT_DESC(qhl_request_remote_writes, "event=0x20,umask=0x08"),
1002 INTEL_UNCORE_EVENT_DESC(qhl_request_local_reads, "event=0x20,umask=0x10"),
1003 INTEL_UNCORE_EVENT_DESC(qhl_request_local_writes, "event=0x20,umask=0x20"),
1004 { /* end: all zeroes */ },
1005 };
1006
1007 static struct intel_uncore_ops nhm_uncore_msr_ops = {
1008 .disable_box = nhm_uncore_msr_disable_box,
1009 .enable_box = nhm_uncore_msr_enable_box,
1010 .disable_event = snb_uncore_msr_disable_event,
1011 .enable_event = nhm_uncore_msr_enable_event,
1012 .read_counter = uncore_msr_read_counter,
1013 };
1014
1015 static struct intel_uncore_type nhm_uncore = {
1016 .name = "",
1017 .num_counters = 8,
1018 .num_boxes = 1,
1019 .perf_ctr_bits = 48,
1020 .fixed_ctr_bits = 48,
1021 .event_ctl = NHM_UNC_PERFEVTSEL0,
1022 .perf_ctr = NHM_UNC_UNCORE_PMC0,
1023 .fixed_ctr = NHM_UNC_FIXED_CTR,
1024 .fixed_ctl = NHM_UNC_FIXED_CTR_CTRL,
1025 .event_mask = NHM_UNC_RAW_EVENT_MASK,
1026 .event_descs = nhm_uncore_events,
1027 .ops = &nhm_uncore_msr_ops,
1028 .format_group = &nhm_uncore_format_group,
1029 };
1030
1031 static struct intel_uncore_type *nhm_msr_uncores[] = {
1032 &nhm_uncore,
1033 NULL,
1034 };
1035
nhm_uncore_cpu_init(void)1036 void nhm_uncore_cpu_init(void)
1037 {
1038 uncore_msr_uncores = nhm_msr_uncores;
1039 }
1040
1041 /* end of Nehalem uncore support */
1042