1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * PCM3168A codec driver
4 *
5 * Copyright (C) 2015 Imagination Technologies Ltd.
6 *
7 * Author: Damien Horsley <Damien.Horsley@imgtec.com>
8 */
9
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/module.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/regulator/consumer.h>
15
16 #include <sound/pcm_params.h>
17 #include <sound/soc.h>
18 #include <sound/tlv.h>
19
20 #include "pcm3168a.h"
21
22 #define PCM3168A_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
23 SNDRV_PCM_FMTBIT_S24_3LE | \
24 SNDRV_PCM_FMTBIT_S24_LE)
25
26 #define PCM3168A_FMT_I2S 0x0
27 #define PCM3168A_FMT_LEFT_J 0x1
28 #define PCM3168A_FMT_RIGHT_J 0x2
29 #define PCM3168A_FMT_RIGHT_J_16 0x3
30 #define PCM3168A_FMT_DSP_A 0x4
31 #define PCM3168A_FMT_DSP_B 0x5
32 #define PCM3168A_FMT_I2S_TDM 0x6
33 #define PCM3168A_FMT_LEFT_J_TDM 0x7
34 #define PCM3168A_FMT_DSP_MASK 0x4
35
36 #define PCM3168A_NUM_SUPPLIES 6
37 static const char *const pcm3168a_supply_names[PCM3168A_NUM_SUPPLIES] = {
38 "VDD1",
39 "VDD2",
40 "VCCAD1",
41 "VCCAD2",
42 "VCCDA1",
43 "VCCDA2"
44 };
45
46 #define PCM3168A_DAI_DAC 0
47 #define PCM3168A_DAI_ADC 1
48
49 /* ADC/DAC side parameters */
50 struct pcm3168a_io_params {
51 bool master_mode;
52 unsigned int fmt;
53 int tdm_slots;
54 u32 tdm_mask;
55 int slot_width;
56 };
57
58 struct pcm3168a_priv {
59 struct regulator_bulk_data supplies[PCM3168A_NUM_SUPPLIES];
60 struct regmap *regmap;
61 struct clk *scki;
62 unsigned long sysclk;
63
64 struct pcm3168a_io_params io_params[2];
65 };
66
67 static const char *const pcm3168a_roll_off[] = { "Sharp", "Slow" };
68
69 static SOC_ENUM_SINGLE_DECL(pcm3168a_d1_roll_off, PCM3168A_DAC_OP_FLT,
70 PCM3168A_DAC_FLT_SHIFT, pcm3168a_roll_off);
71 static SOC_ENUM_SINGLE_DECL(pcm3168a_d2_roll_off, PCM3168A_DAC_OP_FLT,
72 PCM3168A_DAC_FLT_SHIFT + 1, pcm3168a_roll_off);
73 static SOC_ENUM_SINGLE_DECL(pcm3168a_d3_roll_off, PCM3168A_DAC_OP_FLT,
74 PCM3168A_DAC_FLT_SHIFT + 2, pcm3168a_roll_off);
75 static SOC_ENUM_SINGLE_DECL(pcm3168a_d4_roll_off, PCM3168A_DAC_OP_FLT,
76 PCM3168A_DAC_FLT_SHIFT + 3, pcm3168a_roll_off);
77
78 static const char *const pcm3168a_volume_type[] = {
79 "Individual", "Master + Individual" };
80
81 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_volume_type, PCM3168A_DAC_ATT_DEMP_ZF,
82 PCM3168A_DAC_ATMDDA_SHIFT, pcm3168a_volume_type);
83
84 static const char *const pcm3168a_att_speed_mult[] = { "2048", "4096" };
85
86 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_att_mult, PCM3168A_DAC_ATT_DEMP_ZF,
87 PCM3168A_DAC_ATSPDA_SHIFT, pcm3168a_att_speed_mult);
88
89 static const char *const pcm3168a_demp[] = {
90 "Disabled", "48khz", "44.1khz", "32khz" };
91
92 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_demp, PCM3168A_DAC_ATT_DEMP_ZF,
93 PCM3168A_DAC_DEMP_SHIFT, pcm3168a_demp);
94
95 static const char *const pcm3168a_zf_func[] = {
96 "DAC 1/2/3/4 AND", "DAC 1/2/3/4 OR", "DAC 1/2/3 AND",
97 "DAC 1/2/3 OR", "DAC 4 AND", "DAC 4 OR" };
98
99 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_zf_func, PCM3168A_DAC_ATT_DEMP_ZF,
100 PCM3168A_DAC_AZRO_SHIFT, pcm3168a_zf_func);
101
102 static const char *const pcm3168a_pol[] = { "Active High", "Active Low" };
103
104 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_zf_pol, PCM3168A_DAC_ATT_DEMP_ZF,
105 PCM3168A_DAC_ATSPDA_SHIFT, pcm3168a_pol);
106
107 static const char *const pcm3168a_con[] = { "Differential", "Single-Ended" };
108
109 static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc1_con, PCM3168A_ADC_SEAD,
110 0, 1, pcm3168a_con);
111 static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc2_con, PCM3168A_ADC_SEAD,
112 2, 3, pcm3168a_con);
113 static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc3_con, PCM3168A_ADC_SEAD,
114 4, 5, pcm3168a_con);
115
116 static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_volume_type, PCM3168A_ADC_ATT_OVF,
117 PCM3168A_ADC_ATMDAD_SHIFT, pcm3168a_volume_type);
118
119 static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_att_mult, PCM3168A_ADC_ATT_OVF,
120 PCM3168A_ADC_ATSPAD_SHIFT, pcm3168a_att_speed_mult);
121
122 static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_ov_pol, PCM3168A_ADC_ATT_OVF,
123 PCM3168A_ADC_OVFP_SHIFT, pcm3168a_pol);
124
125 /* -100db to 0db, register values 0-54 cause mute */
126 static const DECLARE_TLV_DB_SCALE(pcm3168a_dac_tlv, -10050, 50, 1);
127
128 /* -100db to 20db, register values 0-14 cause mute */
129 static const DECLARE_TLV_DB_SCALE(pcm3168a_adc_tlv, -10050, 50, 1);
130
131 static const struct snd_kcontrol_new pcm3168a_snd_controls[] = {
132 SOC_SINGLE("DAC Power-Save Switch", PCM3168A_DAC_PWR_MST_FMT,
133 PCM3168A_DAC_PSMDA_SHIFT, 1, 1),
134 SOC_ENUM("DAC1 Digital Filter roll-off", pcm3168a_d1_roll_off),
135 SOC_ENUM("DAC2 Digital Filter roll-off", pcm3168a_d2_roll_off),
136 SOC_ENUM("DAC3 Digital Filter roll-off", pcm3168a_d3_roll_off),
137 SOC_ENUM("DAC4 Digital Filter roll-off", pcm3168a_d4_roll_off),
138 SOC_DOUBLE("DAC1 Invert Switch", PCM3168A_DAC_INV, 0, 1, 1, 0),
139 SOC_DOUBLE("DAC2 Invert Switch", PCM3168A_DAC_INV, 2, 3, 1, 0),
140 SOC_DOUBLE("DAC3 Invert Switch", PCM3168A_DAC_INV, 4, 5, 1, 0),
141 SOC_DOUBLE("DAC4 Invert Switch", PCM3168A_DAC_INV, 6, 7, 1, 0),
142 SOC_ENUM("DAC Volume Control Type", pcm3168a_dac_volume_type),
143 SOC_ENUM("DAC Volume Rate Multiplier", pcm3168a_dac_att_mult),
144 SOC_ENUM("DAC De-Emphasis", pcm3168a_dac_demp),
145 SOC_ENUM("DAC Zero Flag Function", pcm3168a_dac_zf_func),
146 SOC_ENUM("DAC Zero Flag Polarity", pcm3168a_dac_zf_pol),
147 SOC_SINGLE_RANGE_TLV("Master Playback Volume",
148 PCM3168A_DAC_VOL_MASTER, 0, 54, 255, 0,
149 pcm3168a_dac_tlv),
150 SOC_DOUBLE_R_RANGE_TLV("DAC1 Playback Volume",
151 PCM3168A_DAC_VOL_CHAN_START,
152 PCM3168A_DAC_VOL_CHAN_START + 1,
153 0, 54, 255, 0, pcm3168a_dac_tlv),
154 SOC_DOUBLE_R_RANGE_TLV("DAC2 Playback Volume",
155 PCM3168A_DAC_VOL_CHAN_START + 2,
156 PCM3168A_DAC_VOL_CHAN_START + 3,
157 0, 54, 255, 0, pcm3168a_dac_tlv),
158 SOC_DOUBLE_R_RANGE_TLV("DAC3 Playback Volume",
159 PCM3168A_DAC_VOL_CHAN_START + 4,
160 PCM3168A_DAC_VOL_CHAN_START + 5,
161 0, 54, 255, 0, pcm3168a_dac_tlv),
162 SOC_DOUBLE_R_RANGE_TLV("DAC4 Playback Volume",
163 PCM3168A_DAC_VOL_CHAN_START + 6,
164 PCM3168A_DAC_VOL_CHAN_START + 7,
165 0, 54, 255, 0, pcm3168a_dac_tlv),
166 SOC_SINGLE("ADC1 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB,
167 PCM3168A_ADC_BYP_SHIFT, 1, 1),
168 SOC_SINGLE("ADC2 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB,
169 PCM3168A_ADC_BYP_SHIFT + 1, 1, 1),
170 SOC_SINGLE("ADC3 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB,
171 PCM3168A_ADC_BYP_SHIFT + 2, 1, 1),
172 SOC_ENUM("ADC1 Connection Type", pcm3168a_adc1_con),
173 SOC_ENUM("ADC2 Connection Type", pcm3168a_adc2_con),
174 SOC_ENUM("ADC3 Connection Type", pcm3168a_adc3_con),
175 SOC_DOUBLE("ADC1 Invert Switch", PCM3168A_ADC_INV, 0, 1, 1, 0),
176 SOC_DOUBLE("ADC2 Invert Switch", PCM3168A_ADC_INV, 2, 3, 1, 0),
177 SOC_DOUBLE("ADC3 Invert Switch", PCM3168A_ADC_INV, 4, 5, 1, 0),
178 SOC_DOUBLE("ADC1 Mute Switch", PCM3168A_ADC_MUTE, 0, 1, 1, 0),
179 SOC_DOUBLE("ADC2 Mute Switch", PCM3168A_ADC_MUTE, 2, 3, 1, 0),
180 SOC_DOUBLE("ADC3 Mute Switch", PCM3168A_ADC_MUTE, 4, 5, 1, 0),
181 SOC_ENUM("ADC Volume Control Type", pcm3168a_adc_volume_type),
182 SOC_ENUM("ADC Volume Rate Multiplier", pcm3168a_adc_att_mult),
183 SOC_ENUM("ADC Overflow Flag Polarity", pcm3168a_adc_ov_pol),
184 SOC_SINGLE_RANGE_TLV("Master Capture Volume",
185 PCM3168A_ADC_VOL_MASTER, 0, 14, 255, 0,
186 pcm3168a_adc_tlv),
187 SOC_DOUBLE_R_RANGE_TLV("ADC1 Capture Volume",
188 PCM3168A_ADC_VOL_CHAN_START,
189 PCM3168A_ADC_VOL_CHAN_START + 1,
190 0, 14, 255, 0, pcm3168a_adc_tlv),
191 SOC_DOUBLE_R_RANGE_TLV("ADC2 Capture Volume",
192 PCM3168A_ADC_VOL_CHAN_START + 2,
193 PCM3168A_ADC_VOL_CHAN_START + 3,
194 0, 14, 255, 0, pcm3168a_adc_tlv),
195 SOC_DOUBLE_R_RANGE_TLV("ADC3 Capture Volume",
196 PCM3168A_ADC_VOL_CHAN_START + 4,
197 PCM3168A_ADC_VOL_CHAN_START + 5,
198 0, 14, 255, 0, pcm3168a_adc_tlv)
199 };
200
201 static const struct snd_soc_dapm_widget pcm3168a_dapm_widgets[] = {
202 SND_SOC_DAPM_DAC("DAC1", "Playback", PCM3168A_DAC_OP_FLT,
203 PCM3168A_DAC_OPEDA_SHIFT, 1),
204 SND_SOC_DAPM_DAC("DAC2", "Playback", PCM3168A_DAC_OP_FLT,
205 PCM3168A_DAC_OPEDA_SHIFT + 1, 1),
206 SND_SOC_DAPM_DAC("DAC3", "Playback", PCM3168A_DAC_OP_FLT,
207 PCM3168A_DAC_OPEDA_SHIFT + 2, 1),
208 SND_SOC_DAPM_DAC("DAC4", "Playback", PCM3168A_DAC_OP_FLT,
209 PCM3168A_DAC_OPEDA_SHIFT + 3, 1),
210
211 SND_SOC_DAPM_OUTPUT("AOUT1L"),
212 SND_SOC_DAPM_OUTPUT("AOUT1R"),
213 SND_SOC_DAPM_OUTPUT("AOUT2L"),
214 SND_SOC_DAPM_OUTPUT("AOUT2R"),
215 SND_SOC_DAPM_OUTPUT("AOUT3L"),
216 SND_SOC_DAPM_OUTPUT("AOUT3R"),
217 SND_SOC_DAPM_OUTPUT("AOUT4L"),
218 SND_SOC_DAPM_OUTPUT("AOUT4R"),
219
220 SND_SOC_DAPM_ADC("ADC1", "Capture", PCM3168A_ADC_PWR_HPFB,
221 PCM3168A_ADC_PSVAD_SHIFT, 1),
222 SND_SOC_DAPM_ADC("ADC2", "Capture", PCM3168A_ADC_PWR_HPFB,
223 PCM3168A_ADC_PSVAD_SHIFT + 1, 1),
224 SND_SOC_DAPM_ADC("ADC3", "Capture", PCM3168A_ADC_PWR_HPFB,
225 PCM3168A_ADC_PSVAD_SHIFT + 2, 1),
226
227 SND_SOC_DAPM_INPUT("AIN1L"),
228 SND_SOC_DAPM_INPUT("AIN1R"),
229 SND_SOC_DAPM_INPUT("AIN2L"),
230 SND_SOC_DAPM_INPUT("AIN2R"),
231 SND_SOC_DAPM_INPUT("AIN3L"),
232 SND_SOC_DAPM_INPUT("AIN3R")
233 };
234
235 static const struct snd_soc_dapm_route pcm3168a_dapm_routes[] = {
236 /* Playback */
237 { "AOUT1L", NULL, "DAC1" },
238 { "AOUT1R", NULL, "DAC1" },
239
240 { "AOUT2L", NULL, "DAC2" },
241 { "AOUT2R", NULL, "DAC2" },
242
243 { "AOUT3L", NULL, "DAC3" },
244 { "AOUT3R", NULL, "DAC3" },
245
246 { "AOUT4L", NULL, "DAC4" },
247 { "AOUT4R", NULL, "DAC4" },
248
249 /* Capture */
250 { "ADC1", NULL, "AIN1L" },
251 { "ADC1", NULL, "AIN1R" },
252
253 { "ADC2", NULL, "AIN2L" },
254 { "ADC2", NULL, "AIN2R" },
255
256 { "ADC3", NULL, "AIN3L" },
257 { "ADC3", NULL, "AIN3R" }
258 };
259
260 static unsigned int pcm3168a_scki_ratios[] = {
261 768,
262 512,
263 384,
264 256,
265 192,
266 128
267 };
268
269 #define PCM3168A_NUM_SCKI_RATIOS_DAC ARRAY_SIZE(pcm3168a_scki_ratios)
270 #define PCM3168A_NUM_SCKI_RATIOS_ADC (ARRAY_SIZE(pcm3168a_scki_ratios) - 2)
271
272 #define PCM3168A_MAX_SYSCLK 36864000
273
pcm3168a_reset(struct pcm3168a_priv * pcm3168a)274 static int pcm3168a_reset(struct pcm3168a_priv *pcm3168a)
275 {
276 int ret;
277
278 ret = regmap_write(pcm3168a->regmap, PCM3168A_RST_SMODE, 0);
279 if (ret)
280 return ret;
281
282 /* Internal reset is de-asserted after 3846 SCKI cycles */
283 msleep(DIV_ROUND_UP(3846 * 1000, pcm3168a->sysclk));
284
285 return regmap_write(pcm3168a->regmap, PCM3168A_RST_SMODE,
286 PCM3168A_MRST_MASK | PCM3168A_SRST_MASK);
287 }
288
pcm3168a_digital_mute(struct snd_soc_dai * dai,int mute)289 static int pcm3168a_digital_mute(struct snd_soc_dai *dai, int mute)
290 {
291 struct snd_soc_component *component = dai->component;
292 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component);
293
294 regmap_write(pcm3168a->regmap, PCM3168A_DAC_MUTE, mute ? 0xff : 0);
295
296 return 0;
297 }
298
pcm3168a_set_dai_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)299 static int pcm3168a_set_dai_sysclk(struct snd_soc_dai *dai,
300 int clk_id, unsigned int freq, int dir)
301 {
302 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(dai->component);
303 int ret;
304
305 /*
306 * Some sound card sets 0 Hz as reset,
307 * but it is impossible to set. Ignore it here
308 */
309 if (freq == 0)
310 return 0;
311
312 if (freq > PCM3168A_MAX_SYSCLK)
313 return -EINVAL;
314
315 ret = clk_set_rate(pcm3168a->scki, freq);
316 if (ret)
317 return ret;
318
319 pcm3168a->sysclk = freq;
320
321 return 0;
322 }
323
pcm3168a_set_dai_fmt(struct snd_soc_dai * dai,unsigned int format)324 static int pcm3168a_set_dai_fmt(struct snd_soc_dai *dai, unsigned int format)
325 {
326 struct snd_soc_component *component = dai->component;
327 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component);
328 u32 fmt, reg, mask, shift;
329 bool master_mode;
330
331 switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
332 case SND_SOC_DAIFMT_LEFT_J:
333 fmt = PCM3168A_FMT_LEFT_J;
334 break;
335 case SND_SOC_DAIFMT_I2S:
336 fmt = PCM3168A_FMT_I2S;
337 break;
338 case SND_SOC_DAIFMT_RIGHT_J:
339 fmt = PCM3168A_FMT_RIGHT_J;
340 break;
341 case SND_SOC_DAIFMT_DSP_A:
342 fmt = PCM3168A_FMT_DSP_A;
343 break;
344 case SND_SOC_DAIFMT_DSP_B:
345 fmt = PCM3168A_FMT_DSP_B;
346 break;
347 default:
348 dev_err(component->dev, "unsupported dai format\n");
349 return -EINVAL;
350 }
351
352 switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
353 case SND_SOC_DAIFMT_CBS_CFS:
354 master_mode = false;
355 break;
356 case SND_SOC_DAIFMT_CBM_CFM:
357 master_mode = true;
358 break;
359 default:
360 dev_err(component->dev, "unsupported master/slave mode\n");
361 return -EINVAL;
362 }
363
364 switch (format & SND_SOC_DAIFMT_INV_MASK) {
365 case SND_SOC_DAIFMT_NB_NF:
366 break;
367 default:
368 return -EINVAL;
369 }
370
371 if (dai->id == PCM3168A_DAI_DAC) {
372 reg = PCM3168A_DAC_PWR_MST_FMT;
373 mask = PCM3168A_DAC_FMT_MASK;
374 shift = PCM3168A_DAC_FMT_SHIFT;
375 } else {
376 reg = PCM3168A_ADC_MST_FMT;
377 mask = PCM3168A_ADC_FMTAD_MASK;
378 shift = PCM3168A_ADC_FMTAD_SHIFT;
379 }
380
381 pcm3168a->io_params[dai->id].master_mode = master_mode;
382 pcm3168a->io_params[dai->id].fmt = fmt;
383
384 regmap_update_bits(pcm3168a->regmap, reg, mask, fmt << shift);
385
386 return 0;
387 }
388
pcm3168a_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)389 static int pcm3168a_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
390 unsigned int rx_mask, int slots,
391 int slot_width)
392 {
393 struct snd_soc_component *component = dai->component;
394 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component);
395 struct pcm3168a_io_params *io_params = &pcm3168a->io_params[dai->id];
396
397 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
398 dev_err(component->dev,
399 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
400 tx_mask, rx_mask, slots);
401 return -EINVAL;
402 }
403
404 if (slot_width &&
405 (slot_width != 16 && slot_width != 24 && slot_width != 32 )) {
406 dev_err(component->dev, "Unsupported slot_width %d\n",
407 slot_width);
408 return -EINVAL;
409 }
410
411 io_params->tdm_slots = slots;
412 io_params->slot_width = slot_width;
413 /* Ignore the not relevant mask for the DAI/direction */
414 if (dai->id == PCM3168A_DAI_DAC)
415 io_params->tdm_mask = tx_mask;
416 else
417 io_params->tdm_mask = rx_mask;
418
419 return 0;
420 }
421
pcm3168a_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)422 static int pcm3168a_hw_params(struct snd_pcm_substream *substream,
423 struct snd_pcm_hw_params *params,
424 struct snd_soc_dai *dai)
425 {
426 struct snd_soc_component *component = dai->component;
427 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component);
428 struct pcm3168a_io_params *io_params = &pcm3168a->io_params[dai->id];
429 bool master_mode;
430 u32 val, mask, shift, reg;
431 unsigned int rate, fmt, ratio, max_ratio;
432 unsigned int tdm_slots;
433 int i, slot_width;
434
435 rate = params_rate(params);
436
437 ratio = pcm3168a->sysclk / rate;
438
439 if (dai->id == PCM3168A_DAI_DAC) {
440 max_ratio = PCM3168A_NUM_SCKI_RATIOS_DAC;
441 reg = PCM3168A_DAC_PWR_MST_FMT;
442 mask = PCM3168A_DAC_MSDA_MASK;
443 shift = PCM3168A_DAC_MSDA_SHIFT;
444 } else {
445 max_ratio = PCM3168A_NUM_SCKI_RATIOS_ADC;
446 reg = PCM3168A_ADC_MST_FMT;
447 mask = PCM3168A_ADC_MSAD_MASK;
448 shift = PCM3168A_ADC_MSAD_SHIFT;
449 }
450
451 master_mode = io_params->master_mode;
452 fmt = io_params->fmt;
453
454 for (i = 0; i < max_ratio; i++) {
455 if (pcm3168a_scki_ratios[i] == ratio)
456 break;
457 }
458
459 if (i == max_ratio) {
460 dev_err(component->dev, "unsupported sysclk ratio\n");
461 return -EINVAL;
462 }
463
464 if (io_params->slot_width)
465 slot_width = io_params->slot_width;
466 else
467 slot_width = params_width(params);
468
469 switch (slot_width) {
470 case 16:
471 if (master_mode || (fmt != PCM3168A_FMT_RIGHT_J)) {
472 dev_err(component->dev, "16-bit slots are supported only for slave mode using right justified\n");
473 return -EINVAL;
474 }
475 fmt = PCM3168A_FMT_RIGHT_J_16;
476 break;
477 case 24:
478 if (master_mode || (fmt & PCM3168A_FMT_DSP_MASK)) {
479 dev_err(component->dev, "24-bit slots not supported in master mode, or slave mode using DSP\n");
480 return -EINVAL;
481 }
482 break;
483 case 32:
484 break;
485 default:
486 dev_err(component->dev, "unsupported frame size: %d\n", slot_width);
487 return -EINVAL;
488 }
489
490 if (io_params->tdm_slots)
491 tdm_slots = io_params->tdm_slots;
492 else
493 tdm_slots = params_channels(params);
494
495 /*
496 * Switch the codec to TDM mode when more than 2 TDM slots are needed
497 * for the stream.
498 * If pcm3168a->tdm_slots is not set or set to more than 2 (8/6 usually)
499 * then DIN1/DOUT1 is used in TDM mode.
500 * If pcm3168a->tdm_slots is set to 2 then DIN1/2/3/4 and DOUT1/2/3 is
501 * used in normal mode, no need to switch to TDM modes.
502 */
503 if (tdm_slots > 2) {
504 switch (fmt) {
505 case PCM3168A_FMT_I2S:
506 case PCM3168A_FMT_DSP_A:
507 fmt = PCM3168A_FMT_I2S_TDM;
508 break;
509 case PCM3168A_FMT_LEFT_J:
510 case PCM3168A_FMT_DSP_B:
511 fmt = PCM3168A_FMT_LEFT_J_TDM;
512 break;
513 default:
514 dev_err(component->dev,
515 "TDM is supported under DSP/I2S/Left_J only\n");
516 return -EINVAL;
517 }
518 }
519
520 if (master_mode)
521 val = ((i + 1) << shift);
522 else
523 val = 0;
524
525 regmap_update_bits(pcm3168a->regmap, reg, mask, val);
526
527 if (dai->id == PCM3168A_DAI_DAC) {
528 mask = PCM3168A_DAC_FMT_MASK;
529 shift = PCM3168A_DAC_FMT_SHIFT;
530 } else {
531 mask = PCM3168A_ADC_FMTAD_MASK;
532 shift = PCM3168A_ADC_FMTAD_SHIFT;
533 }
534
535 regmap_update_bits(pcm3168a->regmap, reg, mask, fmt << shift);
536
537 return 0;
538 }
539
pcm3168a_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)540 static int pcm3168a_startup(struct snd_pcm_substream *substream,
541 struct snd_soc_dai *dai)
542 {
543 struct snd_soc_component *component = dai->component;
544 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component);
545 unsigned int sample_min;
546 unsigned int channel_max;
547 unsigned int channel_maxs[] = {
548 8, /* DAC */
549 6 /* ADC */
550 };
551
552 /*
553 * Available Data Bits
554 *
555 * RIGHT_J : 24 / 16
556 * LEFT_J : 24
557 * I2S : 24
558 *
559 * TDM available
560 *
561 * I2S
562 * LEFT_J
563 */
564 switch (pcm3168a->io_params[dai->id].fmt) {
565 case PCM3168A_FMT_RIGHT_J:
566 sample_min = 16;
567 channel_max = 2;
568 break;
569 case PCM3168A_FMT_LEFT_J:
570 case PCM3168A_FMT_I2S:
571 case PCM3168A_FMT_DSP_A:
572 case PCM3168A_FMT_DSP_B:
573 sample_min = 24;
574 channel_max = channel_maxs[dai->id];
575 break;
576 default:
577 sample_min = 24;
578 channel_max = 2;
579 }
580
581 snd_pcm_hw_constraint_minmax(substream->runtime,
582 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
583 sample_min, 32);
584
585 /* Allow all channels in multi DIN/DOUT mode */
586 if (pcm3168a->io_params[dai->id].tdm_slots == 2)
587 channel_max = channel_maxs[dai->id];
588
589 snd_pcm_hw_constraint_minmax(substream->runtime,
590 SNDRV_PCM_HW_PARAM_CHANNELS,
591 2, channel_max);
592
593 return 0;
594 }
595 static const struct snd_soc_dai_ops pcm3168a_dai_ops = {
596 .startup = pcm3168a_startup,
597 .set_fmt = pcm3168a_set_dai_fmt,
598 .set_sysclk = pcm3168a_set_dai_sysclk,
599 .hw_params = pcm3168a_hw_params,
600 .digital_mute = pcm3168a_digital_mute,
601 .set_tdm_slot = pcm3168a_set_tdm_slot,
602 };
603
604 static struct snd_soc_dai_driver pcm3168a_dais[] = {
605 {
606 .name = "pcm3168a-dac",
607 .id = PCM3168A_DAI_DAC,
608 .playback = {
609 .stream_name = "Playback",
610 .channels_min = 1,
611 .channels_max = 8,
612 .rates = SNDRV_PCM_RATE_8000_192000,
613 .formats = PCM3168A_FORMATS
614 },
615 .ops = &pcm3168a_dai_ops
616 },
617 {
618 .name = "pcm3168a-adc",
619 .id = PCM3168A_DAI_ADC,
620 .capture = {
621 .stream_name = "Capture",
622 .channels_min = 1,
623 .channels_max = 6,
624 .rates = SNDRV_PCM_RATE_8000_96000,
625 .formats = PCM3168A_FORMATS
626 },
627 .ops = &pcm3168a_dai_ops
628 },
629 };
630
631 static const struct reg_default pcm3168a_reg_default[] = {
632 { PCM3168A_RST_SMODE, PCM3168A_MRST_MASK | PCM3168A_SRST_MASK },
633 { PCM3168A_DAC_PWR_MST_FMT, 0x00 },
634 { PCM3168A_DAC_OP_FLT, 0x00 },
635 { PCM3168A_DAC_INV, 0x00 },
636 { PCM3168A_DAC_MUTE, 0x00 },
637 { PCM3168A_DAC_ZERO, 0x00 },
638 { PCM3168A_DAC_ATT_DEMP_ZF, 0x00 },
639 { PCM3168A_DAC_VOL_MASTER, 0xff },
640 { PCM3168A_DAC_VOL_CHAN_START, 0xff },
641 { PCM3168A_DAC_VOL_CHAN_START + 1, 0xff },
642 { PCM3168A_DAC_VOL_CHAN_START + 2, 0xff },
643 { PCM3168A_DAC_VOL_CHAN_START + 3, 0xff },
644 { PCM3168A_DAC_VOL_CHAN_START + 4, 0xff },
645 { PCM3168A_DAC_VOL_CHAN_START + 5, 0xff },
646 { PCM3168A_DAC_VOL_CHAN_START + 6, 0xff },
647 { PCM3168A_DAC_VOL_CHAN_START + 7, 0xff },
648 { PCM3168A_ADC_SMODE, 0x00 },
649 { PCM3168A_ADC_MST_FMT, 0x00 },
650 { PCM3168A_ADC_PWR_HPFB, 0x00 },
651 { PCM3168A_ADC_SEAD, 0x00 },
652 { PCM3168A_ADC_INV, 0x00 },
653 { PCM3168A_ADC_MUTE, 0x00 },
654 { PCM3168A_ADC_OV, 0x00 },
655 { PCM3168A_ADC_ATT_OVF, 0x00 },
656 { PCM3168A_ADC_VOL_MASTER, 0xd3 },
657 { PCM3168A_ADC_VOL_CHAN_START, 0xd3 },
658 { PCM3168A_ADC_VOL_CHAN_START + 1, 0xd3 },
659 { PCM3168A_ADC_VOL_CHAN_START + 2, 0xd3 },
660 { PCM3168A_ADC_VOL_CHAN_START + 3, 0xd3 },
661 { PCM3168A_ADC_VOL_CHAN_START + 4, 0xd3 },
662 { PCM3168A_ADC_VOL_CHAN_START + 5, 0xd3 }
663 };
664
pcm3168a_readable_register(struct device * dev,unsigned int reg)665 static bool pcm3168a_readable_register(struct device *dev, unsigned int reg)
666 {
667 if (reg >= PCM3168A_RST_SMODE)
668 return true;
669 else
670 return false;
671 }
672
pcm3168a_volatile_register(struct device * dev,unsigned int reg)673 static bool pcm3168a_volatile_register(struct device *dev, unsigned int reg)
674 {
675 switch (reg) {
676 case PCM3168A_DAC_ZERO:
677 case PCM3168A_ADC_OV:
678 return true;
679 default:
680 return false;
681 }
682 }
683
pcm3168a_writeable_register(struct device * dev,unsigned int reg)684 static bool pcm3168a_writeable_register(struct device *dev, unsigned int reg)
685 {
686 if (reg < PCM3168A_RST_SMODE)
687 return false;
688
689 switch (reg) {
690 case PCM3168A_DAC_ZERO:
691 case PCM3168A_ADC_OV:
692 return false;
693 default:
694 return true;
695 }
696 }
697
698 const struct regmap_config pcm3168a_regmap = {
699 .reg_bits = 8,
700 .val_bits = 8,
701
702 .max_register = PCM3168A_ADC_VOL_CHAN_START + 5,
703 .reg_defaults = pcm3168a_reg_default,
704 .num_reg_defaults = ARRAY_SIZE(pcm3168a_reg_default),
705 .readable_reg = pcm3168a_readable_register,
706 .volatile_reg = pcm3168a_volatile_register,
707 .writeable_reg = pcm3168a_writeable_register,
708 .cache_type = REGCACHE_FLAT
709 };
710 EXPORT_SYMBOL_GPL(pcm3168a_regmap);
711
712 static const struct snd_soc_component_driver pcm3168a_driver = {
713 .controls = pcm3168a_snd_controls,
714 .num_controls = ARRAY_SIZE(pcm3168a_snd_controls),
715 .dapm_widgets = pcm3168a_dapm_widgets,
716 .num_dapm_widgets = ARRAY_SIZE(pcm3168a_dapm_widgets),
717 .dapm_routes = pcm3168a_dapm_routes,
718 .num_dapm_routes = ARRAY_SIZE(pcm3168a_dapm_routes),
719 .use_pmdown_time = 1,
720 .endianness = 1,
721 .non_legacy_dai_naming = 1,
722 };
723
pcm3168a_probe(struct device * dev,struct regmap * regmap)724 int pcm3168a_probe(struct device *dev, struct regmap *regmap)
725 {
726 struct pcm3168a_priv *pcm3168a;
727 int ret, i;
728
729 pcm3168a = devm_kzalloc(dev, sizeof(*pcm3168a), GFP_KERNEL);
730 if (pcm3168a == NULL)
731 return -ENOMEM;
732
733 dev_set_drvdata(dev, pcm3168a);
734
735 pcm3168a->scki = devm_clk_get(dev, "scki");
736 if (IS_ERR(pcm3168a->scki)) {
737 ret = PTR_ERR(pcm3168a->scki);
738 if (ret != -EPROBE_DEFER)
739 dev_err(dev, "failed to acquire clock 'scki': %d\n", ret);
740 return ret;
741 }
742
743 ret = clk_prepare_enable(pcm3168a->scki);
744 if (ret) {
745 dev_err(dev, "Failed to enable mclk: %d\n", ret);
746 return ret;
747 }
748
749 pcm3168a->sysclk = clk_get_rate(pcm3168a->scki);
750
751 for (i = 0; i < ARRAY_SIZE(pcm3168a->supplies); i++)
752 pcm3168a->supplies[i].supply = pcm3168a_supply_names[i];
753
754 ret = devm_regulator_bulk_get(dev,
755 ARRAY_SIZE(pcm3168a->supplies), pcm3168a->supplies);
756 if (ret) {
757 if (ret != -EPROBE_DEFER)
758 dev_err(dev, "failed to request supplies: %d\n", ret);
759 goto err_clk;
760 }
761
762 ret = regulator_bulk_enable(ARRAY_SIZE(pcm3168a->supplies),
763 pcm3168a->supplies);
764 if (ret) {
765 dev_err(dev, "failed to enable supplies: %d\n", ret);
766 goto err_clk;
767 }
768
769 pcm3168a->regmap = regmap;
770 if (IS_ERR(pcm3168a->regmap)) {
771 ret = PTR_ERR(pcm3168a->regmap);
772 dev_err(dev, "failed to allocate regmap: %d\n", ret);
773 goto err_regulator;
774 }
775
776 ret = pcm3168a_reset(pcm3168a);
777 if (ret) {
778 dev_err(dev, "Failed to reset device: %d\n", ret);
779 goto err_regulator;
780 }
781
782 pm_runtime_set_active(dev);
783 pm_runtime_enable(dev);
784 pm_runtime_idle(dev);
785
786 ret = devm_snd_soc_register_component(dev, &pcm3168a_driver, pcm3168a_dais,
787 ARRAY_SIZE(pcm3168a_dais));
788 if (ret) {
789 dev_err(dev, "failed to register component: %d\n", ret);
790 goto err_regulator;
791 }
792
793 return 0;
794
795 err_regulator:
796 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies),
797 pcm3168a->supplies);
798 err_clk:
799 clk_disable_unprepare(pcm3168a->scki);
800
801 return ret;
802 }
803 EXPORT_SYMBOL_GPL(pcm3168a_probe);
804
pcm3168a_disable(struct device * dev)805 static void pcm3168a_disable(struct device *dev)
806 {
807 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev);
808
809 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies),
810 pcm3168a->supplies);
811 clk_disable_unprepare(pcm3168a->scki);
812 }
813
pcm3168a_remove(struct device * dev)814 void pcm3168a_remove(struct device *dev)
815 {
816 pm_runtime_disable(dev);
817 #ifndef CONFIG_PM
818 pcm3168a_disable(dev);
819 #endif
820 }
821 EXPORT_SYMBOL_GPL(pcm3168a_remove);
822
823 #ifdef CONFIG_PM
pcm3168a_rt_resume(struct device * dev)824 static int pcm3168a_rt_resume(struct device *dev)
825 {
826 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev);
827 int ret;
828
829 ret = clk_prepare_enable(pcm3168a->scki);
830 if (ret) {
831 dev_err(dev, "Failed to enable mclk: %d\n", ret);
832 return ret;
833 }
834
835 ret = regulator_bulk_enable(ARRAY_SIZE(pcm3168a->supplies),
836 pcm3168a->supplies);
837 if (ret) {
838 dev_err(dev, "Failed to enable supplies: %d\n", ret);
839 goto err_clk;
840 }
841
842 ret = pcm3168a_reset(pcm3168a);
843 if (ret) {
844 dev_err(dev, "Failed to reset device: %d\n", ret);
845 goto err_regulator;
846 }
847
848 regcache_cache_only(pcm3168a->regmap, false);
849
850 regcache_mark_dirty(pcm3168a->regmap);
851
852 ret = regcache_sync(pcm3168a->regmap);
853 if (ret) {
854 dev_err(dev, "Failed to sync regmap: %d\n", ret);
855 goto err_regulator;
856 }
857
858 return 0;
859
860 err_regulator:
861 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies),
862 pcm3168a->supplies);
863 err_clk:
864 clk_disable_unprepare(pcm3168a->scki);
865
866 return ret;
867 }
868
pcm3168a_rt_suspend(struct device * dev)869 static int pcm3168a_rt_suspend(struct device *dev)
870 {
871 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev);
872
873 regcache_cache_only(pcm3168a->regmap, true);
874
875 pcm3168a_disable(dev);
876
877 return 0;
878 }
879 #endif
880
881 const struct dev_pm_ops pcm3168a_pm_ops = {
882 SET_RUNTIME_PM_OPS(pcm3168a_rt_suspend, pcm3168a_rt_resume, NULL)
883 };
884 EXPORT_SYMBOL_GPL(pcm3168a_pm_ops);
885
886 MODULE_DESCRIPTION("PCM3168A codec driver");
887 MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>");
888 MODULE_LICENSE("GPL v2");
889