1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver
4 //
5 // Copyright (C) 2013 Freescale Semiconductor, Inc.
6 //
7 // Based on stmp3xxx_spdif_dai.c
8 // Vladimir Barinov <vbarinov@embeddedalley.com>
9 // Copyright 2008 SigmaTel, Inc
10 // Copyright 2008 Embedded Alley Solutions, Inc
11
12 #include <linux/bitrev.h>
13 #include <linux/clk.h>
14 #include <linux/module.h>
15 #include <linux/of_address.h>
16 #include <linux/of_device.h>
17 #include <linux/of_irq.h>
18 #include <linux/regmap.h>
19
20 #include <sound/asoundef.h>
21 #include <sound/dmaengine_pcm.h>
22 #include <sound/soc.h>
23
24 #include "fsl_spdif.h"
25 #include "imx-pcm.h"
26
27 #define FSL_SPDIF_TXFIFO_WML 0x8
28 #define FSL_SPDIF_RXFIFO_WML 0x8
29
30 #define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC)
31 #define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |\
32 INT_URX_OV | INT_QRX_FUL | INT_QRX_OV |\
33 INT_UQ_SYNC | INT_UQ_ERR | INT_RXFIFO_RESYNC |\
34 INT_LOSS_LOCK | INT_DPLL_LOCKED)
35
36 #define SIE_INTR_FOR(tx) (tx ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE)
37
38 /* Index list for the values that has if (DPLL Locked) condition */
39 static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb };
40 #define SRPC_NODPLL_START1 0x5
41 #define SRPC_NODPLL_START2 0xc
42
43 #define DEFAULT_RXCLK_SRC 1
44
45 /*
46 * SPDIF control structure
47 * Defines channel status, subcode and Q sub
48 */
49 struct spdif_mixer_control {
50 /* spinlock to access control data */
51 spinlock_t ctl_lock;
52
53 /* IEC958 channel tx status bit */
54 unsigned char ch_status[4];
55
56 /* User bits */
57 unsigned char subcode[2 * SPDIF_UBITS_SIZE];
58
59 /* Q subcode part of user bits */
60 unsigned char qsub[2 * SPDIF_QSUB_SIZE];
61
62 /* Buffer offset for U/Q */
63 u32 upos;
64 u32 qpos;
65
66 /* Ready buffer index of the two buffers */
67 u32 ready_buf;
68 };
69
70 /**
71 * fsl_spdif_priv: Freescale SPDIF private data
72 *
73 * @fsl_spdif_control: SPDIF control data
74 * @cpu_dai_drv: cpu dai driver
75 * @pdev: platform device pointer
76 * @regmap: regmap handler
77 * @dpll_locked: dpll lock flag
78 * @txrate: the best rates for playback
79 * @txclk_df: STC_TXCLK_DF dividers value for playback
80 * @sysclk_df: STC_SYSCLK_DF dividers value for playback
81 * @txclk_src: STC_TXCLK_SRC values for playback
82 * @rxclk_src: SRPC_CLKSRC_SEL values for capture
83 * @txclk: tx clock sources for playback
84 * @rxclk: rx clock sources for capture
85 * @coreclk: core clock for register access via DMA
86 * @sysclk: system clock for rx clock rate measurement
87 * @spbaclk: SPBA clock (optional, depending on SoC design)
88 * @dma_params_tx: DMA parameters for transmit channel
89 * @dma_params_rx: DMA parameters for receive channel
90 */
91 struct fsl_spdif_priv {
92 struct spdif_mixer_control fsl_spdif_control;
93 struct snd_soc_dai_driver cpu_dai_drv;
94 struct platform_device *pdev;
95 struct regmap *regmap;
96 bool dpll_locked;
97 u32 txrate[SPDIF_TXRATE_MAX];
98 u8 txclk_df[SPDIF_TXRATE_MAX];
99 u16 sysclk_df[SPDIF_TXRATE_MAX];
100 u8 txclk_src[SPDIF_TXRATE_MAX];
101 u8 rxclk_src;
102 struct clk *txclk[SPDIF_TXRATE_MAX];
103 struct clk *rxclk;
104 struct clk *coreclk;
105 struct clk *sysclk;
106 struct clk *spbaclk;
107 struct snd_dmaengine_dai_dma_data dma_params_tx;
108 struct snd_dmaengine_dai_dma_data dma_params_rx;
109 /* regcache for SRPC */
110 u32 regcache_srpc;
111 };
112
113 /* DPLL locked and lock loss interrupt handler */
spdif_irq_dpll_lock(struct fsl_spdif_priv * spdif_priv)114 static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv)
115 {
116 struct regmap *regmap = spdif_priv->regmap;
117 struct platform_device *pdev = spdif_priv->pdev;
118 u32 locked;
119
120 regmap_read(regmap, REG_SPDIF_SRPC, &locked);
121 locked &= SRPC_DPLL_LOCKED;
122
123 dev_dbg(&pdev->dev, "isr: Rx dpll %s \n",
124 locked ? "locked" : "loss lock");
125
126 spdif_priv->dpll_locked = locked ? true : false;
127 }
128
129 /* Receiver found illegal symbol interrupt handler */
spdif_irq_sym_error(struct fsl_spdif_priv * spdif_priv)130 static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv)
131 {
132 struct regmap *regmap = spdif_priv->regmap;
133 struct platform_device *pdev = spdif_priv->pdev;
134
135 dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n");
136
137 /* Clear illegal symbol if DPLL unlocked since no audio stream */
138 if (!spdif_priv->dpll_locked)
139 regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0);
140 }
141
142 /* U/Q Channel receive register full */
spdif_irq_uqrx_full(struct fsl_spdif_priv * spdif_priv,char name)143 static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name)
144 {
145 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
146 struct regmap *regmap = spdif_priv->regmap;
147 struct platform_device *pdev = spdif_priv->pdev;
148 u32 *pos, size, val, reg;
149
150 switch (name) {
151 case 'U':
152 pos = &ctrl->upos;
153 size = SPDIF_UBITS_SIZE;
154 reg = REG_SPDIF_SRU;
155 break;
156 case 'Q':
157 pos = &ctrl->qpos;
158 size = SPDIF_QSUB_SIZE;
159 reg = REG_SPDIF_SRQ;
160 break;
161 default:
162 dev_err(&pdev->dev, "unsupported channel name\n");
163 return;
164 }
165
166 dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name);
167
168 if (*pos >= size * 2) {
169 *pos = 0;
170 } else if (unlikely((*pos % size) + 3 > size)) {
171 dev_err(&pdev->dev, "User bit receive buffer overflow\n");
172 return;
173 }
174
175 regmap_read(regmap, reg, &val);
176 ctrl->subcode[*pos++] = val >> 16;
177 ctrl->subcode[*pos++] = val >> 8;
178 ctrl->subcode[*pos++] = val;
179 }
180
181 /* U/Q Channel sync found */
spdif_irq_uq_sync(struct fsl_spdif_priv * spdif_priv)182 static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv)
183 {
184 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
185 struct platform_device *pdev = spdif_priv->pdev;
186
187 dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n");
188
189 /* U/Q buffer reset */
190 if (ctrl->qpos == 0)
191 return;
192
193 /* Set ready to this buffer */
194 ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1;
195 }
196
197 /* U/Q Channel framing error */
spdif_irq_uq_err(struct fsl_spdif_priv * spdif_priv)198 static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv)
199 {
200 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
201 struct regmap *regmap = spdif_priv->regmap;
202 struct platform_device *pdev = spdif_priv->pdev;
203 u32 val;
204
205 dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n");
206
207 /* Read U/Q data to clear the irq and do buffer reset */
208 regmap_read(regmap, REG_SPDIF_SRU, &val);
209 regmap_read(regmap, REG_SPDIF_SRQ, &val);
210
211 /* Drop this U/Q buffer */
212 ctrl->ready_buf = 0;
213 ctrl->upos = 0;
214 ctrl->qpos = 0;
215 }
216
217 /* Get spdif interrupt status and clear the interrupt */
spdif_intr_status_clear(struct fsl_spdif_priv * spdif_priv)218 static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv)
219 {
220 struct regmap *regmap = spdif_priv->regmap;
221 u32 val, val2;
222
223 regmap_read(regmap, REG_SPDIF_SIS, &val);
224 regmap_read(regmap, REG_SPDIF_SIE, &val2);
225
226 regmap_write(regmap, REG_SPDIF_SIC, val & val2);
227
228 return val;
229 }
230
spdif_isr(int irq,void * devid)231 static irqreturn_t spdif_isr(int irq, void *devid)
232 {
233 struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid;
234 struct platform_device *pdev = spdif_priv->pdev;
235 u32 sis;
236
237 sis = spdif_intr_status_clear(spdif_priv);
238
239 if (sis & INT_DPLL_LOCKED)
240 spdif_irq_dpll_lock(spdif_priv);
241
242 if (sis & INT_TXFIFO_UNOV)
243 dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n");
244
245 if (sis & INT_TXFIFO_RESYNC)
246 dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n");
247
248 if (sis & INT_CNEW)
249 dev_dbg(&pdev->dev, "isr: cstatus new\n");
250
251 if (sis & INT_VAL_NOGOOD)
252 dev_dbg(&pdev->dev, "isr: validity flag no good\n");
253
254 if (sis & INT_SYM_ERR)
255 spdif_irq_sym_error(spdif_priv);
256
257 if (sis & INT_BIT_ERR)
258 dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n");
259
260 if (sis & INT_URX_FUL)
261 spdif_irq_uqrx_full(spdif_priv, 'U');
262
263 if (sis & INT_URX_OV)
264 dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n");
265
266 if (sis & INT_QRX_FUL)
267 spdif_irq_uqrx_full(spdif_priv, 'Q');
268
269 if (sis & INT_QRX_OV)
270 dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n");
271
272 if (sis & INT_UQ_SYNC)
273 spdif_irq_uq_sync(spdif_priv);
274
275 if (sis & INT_UQ_ERR)
276 spdif_irq_uq_err(spdif_priv);
277
278 if (sis & INT_RXFIFO_UNOV)
279 dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n");
280
281 if (sis & INT_RXFIFO_RESYNC)
282 dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n");
283
284 if (sis & INT_LOSS_LOCK)
285 spdif_irq_dpll_lock(spdif_priv);
286
287 /* FIXME: Write Tx FIFO to clear TxEm */
288 if (sis & INT_TX_EM)
289 dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n");
290
291 /* FIXME: Read Rx FIFO to clear RxFIFOFul */
292 if (sis & INT_RXFIFO_FUL)
293 dev_dbg(&pdev->dev, "isr: Rx FIFO full\n");
294
295 return IRQ_HANDLED;
296 }
297
spdif_softreset(struct fsl_spdif_priv * spdif_priv)298 static int spdif_softreset(struct fsl_spdif_priv *spdif_priv)
299 {
300 struct regmap *regmap = spdif_priv->regmap;
301 u32 val, cycle = 1000;
302
303 regcache_cache_bypass(regmap, true);
304
305 regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET);
306
307 /*
308 * RESET bit would be cleared after finishing its reset procedure,
309 * which typically lasts 8 cycles. 1000 cycles will keep it safe.
310 */
311 do {
312 regmap_read(regmap, REG_SPDIF_SCR, &val);
313 } while ((val & SCR_SOFT_RESET) && cycle--);
314
315 regcache_cache_bypass(regmap, false);
316 regcache_mark_dirty(regmap);
317 regcache_sync(regmap);
318
319 if (cycle)
320 return 0;
321 else
322 return -EBUSY;
323 }
324
spdif_set_cstatus(struct spdif_mixer_control * ctrl,u8 mask,u8 cstatus)325 static void spdif_set_cstatus(struct spdif_mixer_control *ctrl,
326 u8 mask, u8 cstatus)
327 {
328 ctrl->ch_status[3] &= ~mask;
329 ctrl->ch_status[3] |= cstatus & mask;
330 }
331
spdif_write_channel_status(struct fsl_spdif_priv * spdif_priv)332 static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv)
333 {
334 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
335 struct regmap *regmap = spdif_priv->regmap;
336 struct platform_device *pdev = spdif_priv->pdev;
337 u32 ch_status;
338
339 ch_status = (bitrev8(ctrl->ch_status[0]) << 16) |
340 (bitrev8(ctrl->ch_status[1]) << 8) |
341 bitrev8(ctrl->ch_status[2]);
342 regmap_write(regmap, REG_SPDIF_STCSCH, ch_status);
343
344 dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status);
345
346 ch_status = bitrev8(ctrl->ch_status[3]) << 16;
347 regmap_write(regmap, REG_SPDIF_STCSCL, ch_status);
348
349 dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status);
350 }
351
352 /* Set SPDIF PhaseConfig register for rx clock */
spdif_set_rx_clksrc(struct fsl_spdif_priv * spdif_priv,enum spdif_gainsel gainsel,int dpll_locked)353 static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv,
354 enum spdif_gainsel gainsel, int dpll_locked)
355 {
356 struct regmap *regmap = spdif_priv->regmap;
357 u8 clksrc = spdif_priv->rxclk_src;
358
359 if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX)
360 return -EINVAL;
361
362 regmap_update_bits(regmap, REG_SPDIF_SRPC,
363 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
364 SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel));
365
366 return 0;
367 }
368
spdif_set_sample_rate(struct snd_pcm_substream * substream,int sample_rate)369 static int spdif_set_sample_rate(struct snd_pcm_substream *substream,
370 int sample_rate)
371 {
372 struct snd_soc_pcm_runtime *rtd = substream->private_data;
373 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
374 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
375 struct regmap *regmap = spdif_priv->regmap;
376 struct platform_device *pdev = spdif_priv->pdev;
377 unsigned long csfs = 0;
378 u32 stc, mask, rate;
379 u16 sysclk_df;
380 u8 clk, txclk_df;
381 int ret;
382
383 switch (sample_rate) {
384 case 32000:
385 rate = SPDIF_TXRATE_32000;
386 csfs = IEC958_AES3_CON_FS_32000;
387 break;
388 case 44100:
389 rate = SPDIF_TXRATE_44100;
390 csfs = IEC958_AES3_CON_FS_44100;
391 break;
392 case 48000:
393 rate = SPDIF_TXRATE_48000;
394 csfs = IEC958_AES3_CON_FS_48000;
395 break;
396 case 96000:
397 rate = SPDIF_TXRATE_96000;
398 csfs = IEC958_AES3_CON_FS_96000;
399 break;
400 case 192000:
401 rate = SPDIF_TXRATE_192000;
402 csfs = IEC958_AES3_CON_FS_192000;
403 break;
404 default:
405 dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate);
406 return -EINVAL;
407 }
408
409 clk = spdif_priv->txclk_src[rate];
410 if (clk >= STC_TXCLK_SRC_MAX) {
411 dev_err(&pdev->dev, "tx clock source is out of range\n");
412 return -EINVAL;
413 }
414
415 txclk_df = spdif_priv->txclk_df[rate];
416 if (txclk_df == 0) {
417 dev_err(&pdev->dev, "the txclk_df can't be zero\n");
418 return -EINVAL;
419 }
420
421 sysclk_df = spdif_priv->sysclk_df[rate];
422
423 /* Don't mess up the clocks from other modules */
424 if (clk != STC_TXCLK_SPDIF_ROOT)
425 goto clk_set_bypass;
426
427 /* The S/PDIF block needs a clock of 64 * fs * txclk_df */
428 ret = clk_set_rate(spdif_priv->txclk[rate],
429 64 * sample_rate * txclk_df);
430 if (ret) {
431 dev_err(&pdev->dev, "failed to set tx clock rate\n");
432 return ret;
433 }
434
435 clk_set_bypass:
436 dev_dbg(&pdev->dev, "expected clock rate = %d\n",
437 (64 * sample_rate * txclk_df * sysclk_df));
438 dev_dbg(&pdev->dev, "actual clock rate = %ld\n",
439 clk_get_rate(spdif_priv->txclk[rate]));
440
441 /* set fs field in consumer channel status */
442 spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs);
443
444 /* select clock source and divisor */
445 stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) |
446 STC_TXCLK_DF(txclk_df) | STC_SYSCLK_DF(sysclk_df);
447 mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK |
448 STC_TXCLK_DF_MASK | STC_SYSCLK_DF_MASK;
449 regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc);
450
451 dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n",
452 spdif_priv->txrate[rate], sample_rate);
453
454 return 0;
455 }
456
fsl_spdif_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)457 static int fsl_spdif_startup(struct snd_pcm_substream *substream,
458 struct snd_soc_dai *cpu_dai)
459 {
460 struct snd_soc_pcm_runtime *rtd = substream->private_data;
461 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
462 struct platform_device *pdev = spdif_priv->pdev;
463 struct regmap *regmap = spdif_priv->regmap;
464 u32 scr, mask;
465 int i;
466 int ret;
467
468 /* Reset module and interrupts only for first initialization */
469 if (!cpu_dai->active) {
470 ret = clk_prepare_enable(spdif_priv->coreclk);
471 if (ret) {
472 dev_err(&pdev->dev, "failed to enable core clock\n");
473 return ret;
474 }
475
476 if (!IS_ERR(spdif_priv->spbaclk)) {
477 ret = clk_prepare_enable(spdif_priv->spbaclk);
478 if (ret) {
479 dev_err(&pdev->dev, "failed to enable spba clock\n");
480 goto err_spbaclk;
481 }
482 }
483
484 ret = spdif_softreset(spdif_priv);
485 if (ret) {
486 dev_err(&pdev->dev, "failed to soft reset\n");
487 goto err;
488 }
489
490 /* Disable all the interrupts */
491 regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0);
492 }
493
494 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
495 scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL |
496 SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP |
497 SCR_TXFIFO_FSEL_IF8;
498 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
499 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
500 SCR_TXFIFO_FSEL_MASK;
501 for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
502 ret = clk_prepare_enable(spdif_priv->txclk[i]);
503 if (ret)
504 goto disable_txclk;
505 }
506 } else {
507 scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC;
508 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
509 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
510 ret = clk_prepare_enable(spdif_priv->rxclk);
511 if (ret)
512 goto err;
513 }
514 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
515
516 /* Power up SPDIF module */
517 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0);
518
519 return 0;
520
521 disable_txclk:
522 for (i--; i >= 0; i--)
523 clk_disable_unprepare(spdif_priv->txclk[i]);
524 err:
525 if (!IS_ERR(spdif_priv->spbaclk))
526 clk_disable_unprepare(spdif_priv->spbaclk);
527 err_spbaclk:
528 clk_disable_unprepare(spdif_priv->coreclk);
529
530 return ret;
531 }
532
fsl_spdif_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)533 static void fsl_spdif_shutdown(struct snd_pcm_substream *substream,
534 struct snd_soc_dai *cpu_dai)
535 {
536 struct snd_soc_pcm_runtime *rtd = substream->private_data;
537 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
538 struct regmap *regmap = spdif_priv->regmap;
539 u32 scr, mask, i;
540
541 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
542 scr = 0;
543 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
544 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
545 SCR_TXFIFO_FSEL_MASK;
546 for (i = 0; i < SPDIF_TXRATE_MAX; i++)
547 clk_disable_unprepare(spdif_priv->txclk[i]);
548 } else {
549 scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO;
550 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
551 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
552 clk_disable_unprepare(spdif_priv->rxclk);
553 }
554 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
555
556 /* Power down SPDIF module only if tx&rx are both inactive */
557 if (!cpu_dai->active) {
558 spdif_intr_status_clear(spdif_priv);
559 regmap_update_bits(regmap, REG_SPDIF_SCR,
560 SCR_LOW_POWER, SCR_LOW_POWER);
561 if (!IS_ERR(spdif_priv->spbaclk))
562 clk_disable_unprepare(spdif_priv->spbaclk);
563 clk_disable_unprepare(spdif_priv->coreclk);
564 }
565 }
566
fsl_spdif_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)567 static int fsl_spdif_hw_params(struct snd_pcm_substream *substream,
568 struct snd_pcm_hw_params *params,
569 struct snd_soc_dai *dai)
570 {
571 struct snd_soc_pcm_runtime *rtd = substream->private_data;
572 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
573 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
574 struct platform_device *pdev = spdif_priv->pdev;
575 u32 sample_rate = params_rate(params);
576 int ret = 0;
577
578 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
579 ret = spdif_set_sample_rate(substream, sample_rate);
580 if (ret) {
581 dev_err(&pdev->dev, "%s: set sample rate failed: %d\n",
582 __func__, sample_rate);
583 return ret;
584 }
585 spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK,
586 IEC958_AES3_CON_CLOCK_1000PPM);
587 spdif_write_channel_status(spdif_priv);
588 } else {
589 /* Setup rx clock source */
590 ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1);
591 }
592
593 return ret;
594 }
595
fsl_spdif_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)596 static int fsl_spdif_trigger(struct snd_pcm_substream *substream,
597 int cmd, struct snd_soc_dai *dai)
598 {
599 struct snd_soc_pcm_runtime *rtd = substream->private_data;
600 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
601 struct regmap *regmap = spdif_priv->regmap;
602 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
603 u32 intr = SIE_INTR_FOR(tx);
604 u32 dmaen = SCR_DMA_xX_EN(tx);
605
606 switch (cmd) {
607 case SNDRV_PCM_TRIGGER_START:
608 case SNDRV_PCM_TRIGGER_RESUME:
609 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
610 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr);
611 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen);
612 break;
613 case SNDRV_PCM_TRIGGER_STOP:
614 case SNDRV_PCM_TRIGGER_SUSPEND:
615 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
616 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0);
617 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0);
618 regmap_write(regmap, REG_SPDIF_STL, 0x0);
619 regmap_write(regmap, REG_SPDIF_STR, 0x0);
620 break;
621 default:
622 return -EINVAL;
623 }
624
625 return 0;
626 }
627
628 static const struct snd_soc_dai_ops fsl_spdif_dai_ops = {
629 .startup = fsl_spdif_startup,
630 .hw_params = fsl_spdif_hw_params,
631 .trigger = fsl_spdif_trigger,
632 .shutdown = fsl_spdif_shutdown,
633 };
634
635
636 /*
637 * FSL SPDIF IEC958 controller(mixer) functions
638 *
639 * Channel status get/put control
640 * User bit value get/put control
641 * Valid bit value get control
642 * DPLL lock status get control
643 * User bit sync mode selection control
644 */
645
fsl_spdif_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)646 static int fsl_spdif_info(struct snd_kcontrol *kcontrol,
647 struct snd_ctl_elem_info *uinfo)
648 {
649 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
650 uinfo->count = 1;
651
652 return 0;
653 }
654
fsl_spdif_pb_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * uvalue)655 static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol,
656 struct snd_ctl_elem_value *uvalue)
657 {
658 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
659 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
660 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
661
662 uvalue->value.iec958.status[0] = ctrl->ch_status[0];
663 uvalue->value.iec958.status[1] = ctrl->ch_status[1];
664 uvalue->value.iec958.status[2] = ctrl->ch_status[2];
665 uvalue->value.iec958.status[3] = ctrl->ch_status[3];
666
667 return 0;
668 }
669
fsl_spdif_pb_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * uvalue)670 static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol,
671 struct snd_ctl_elem_value *uvalue)
672 {
673 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
674 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
675 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
676
677 ctrl->ch_status[0] = uvalue->value.iec958.status[0];
678 ctrl->ch_status[1] = uvalue->value.iec958.status[1];
679 ctrl->ch_status[2] = uvalue->value.iec958.status[2];
680 ctrl->ch_status[3] = uvalue->value.iec958.status[3];
681
682 spdif_write_channel_status(spdif_priv);
683
684 return 0;
685 }
686
687 /* Get channel status from SPDIF_RX_CCHAN register */
fsl_spdif_capture_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)688 static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol,
689 struct snd_ctl_elem_value *ucontrol)
690 {
691 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
692 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
693 struct regmap *regmap = spdif_priv->regmap;
694 u32 cstatus, val;
695
696 regmap_read(regmap, REG_SPDIF_SIS, &val);
697 if (!(val & INT_CNEW))
698 return -EAGAIN;
699
700 regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus);
701 ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF;
702 ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF;
703 ucontrol->value.iec958.status[2] = cstatus & 0xFF;
704
705 regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus);
706 ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF;
707 ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF;
708 ucontrol->value.iec958.status[5] = cstatus & 0xFF;
709
710 /* Clear intr */
711 regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW);
712
713 return 0;
714 }
715
716 /*
717 * Get User bits (subcode) from chip value which readed out
718 * in UChannel register.
719 */
fsl_spdif_subcode_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)720 static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol,
721 struct snd_ctl_elem_value *ucontrol)
722 {
723 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
724 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
725 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
726 unsigned long flags;
727 int ret = -EAGAIN;
728
729 spin_lock_irqsave(&ctrl->ctl_lock, flags);
730 if (ctrl->ready_buf) {
731 int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE;
732 memcpy(&ucontrol->value.iec958.subcode[0],
733 &ctrl->subcode[idx], SPDIF_UBITS_SIZE);
734 ret = 0;
735 }
736 spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
737
738 return ret;
739 }
740
741 /* Q-subcode information. The byte size is SPDIF_UBITS_SIZE/8 */
fsl_spdif_qinfo(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)742 static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol,
743 struct snd_ctl_elem_info *uinfo)
744 {
745 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
746 uinfo->count = SPDIF_QSUB_SIZE;
747
748 return 0;
749 }
750
751 /* Get Q subcode from chip value which readed out in QChannel register */
fsl_spdif_qget(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)752 static int fsl_spdif_qget(struct snd_kcontrol *kcontrol,
753 struct snd_ctl_elem_value *ucontrol)
754 {
755 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
756 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
757 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
758 unsigned long flags;
759 int ret = -EAGAIN;
760
761 spin_lock_irqsave(&ctrl->ctl_lock, flags);
762 if (ctrl->ready_buf) {
763 int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE;
764 memcpy(&ucontrol->value.bytes.data[0],
765 &ctrl->qsub[idx], SPDIF_QSUB_SIZE);
766 ret = 0;
767 }
768 spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
769
770 return ret;
771 }
772
773 /* Valid bit information */
fsl_spdif_vbit_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)774 static int fsl_spdif_vbit_info(struct snd_kcontrol *kcontrol,
775 struct snd_ctl_elem_info *uinfo)
776 {
777 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
778 uinfo->count = 1;
779 uinfo->value.integer.min = 0;
780 uinfo->value.integer.max = 1;
781
782 return 0;
783 }
784
785 /* Get valid good bit from interrupt status register */
fsl_spdif_vbit_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)786 static int fsl_spdif_vbit_get(struct snd_kcontrol *kcontrol,
787 struct snd_ctl_elem_value *ucontrol)
788 {
789 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
790 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
791 struct regmap *regmap = spdif_priv->regmap;
792 u32 val;
793
794 regmap_read(regmap, REG_SPDIF_SIS, &val);
795 ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0;
796 regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD);
797
798 return 0;
799 }
800
801 /* DPLL lock information */
fsl_spdif_rxrate_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)802 static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol,
803 struct snd_ctl_elem_info *uinfo)
804 {
805 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
806 uinfo->count = 1;
807 uinfo->value.integer.min = 16000;
808 uinfo->value.integer.max = 96000;
809
810 return 0;
811 }
812
813 static u32 gainsel_multi[GAINSEL_MULTI_MAX] = {
814 24, 16, 12, 8, 6, 4, 3,
815 };
816
817 /* Get RX data clock rate given the SPDIF bus_clk */
spdif_get_rxclk_rate(struct fsl_spdif_priv * spdif_priv,enum spdif_gainsel gainsel)818 static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv,
819 enum spdif_gainsel gainsel)
820 {
821 struct regmap *regmap = spdif_priv->regmap;
822 struct platform_device *pdev = spdif_priv->pdev;
823 u64 tmpval64, busclk_freq = 0;
824 u32 freqmeas, phaseconf;
825 u8 clksrc;
826
827 regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas);
828 regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf);
829
830 clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf;
831
832 /* Get bus clock from system */
833 if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED))
834 busclk_freq = clk_get_rate(spdif_priv->sysclk);
835
836 /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */
837 tmpval64 = (u64) busclk_freq * freqmeas;
838 do_div(tmpval64, gainsel_multi[gainsel] * 1024);
839 do_div(tmpval64, 128 * 1024);
840
841 dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas);
842 dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq);
843 dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64);
844
845 return (int)tmpval64;
846 }
847
848 /*
849 * Get DPLL lock or not info from stable interrupt status register.
850 * User application must use this control to get locked,
851 * then can do next PCM operation
852 */
fsl_spdif_rxrate_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)853 static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol,
854 struct snd_ctl_elem_value *ucontrol)
855 {
856 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
857 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
858 int rate = 0;
859
860 if (spdif_priv->dpll_locked)
861 rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL);
862
863 ucontrol->value.integer.value[0] = rate;
864
865 return 0;
866 }
867
868 /* User bit sync mode info */
fsl_spdif_usync_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)869 static int fsl_spdif_usync_info(struct snd_kcontrol *kcontrol,
870 struct snd_ctl_elem_info *uinfo)
871 {
872 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
873 uinfo->count = 1;
874 uinfo->value.integer.min = 0;
875 uinfo->value.integer.max = 1;
876
877 return 0;
878 }
879
880 /*
881 * User bit sync mode:
882 * 1 CD User channel subcode
883 * 0 Non-CD data
884 */
fsl_spdif_usync_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)885 static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol,
886 struct snd_ctl_elem_value *ucontrol)
887 {
888 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
889 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
890 struct regmap *regmap = spdif_priv->regmap;
891 u32 val;
892
893 regmap_read(regmap, REG_SPDIF_SRCD, &val);
894 ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0;
895
896 return 0;
897 }
898
899 /*
900 * User bit sync mode:
901 * 1 CD User channel subcode
902 * 0 Non-CD data
903 */
fsl_spdif_usync_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)904 static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol,
905 struct snd_ctl_elem_value *ucontrol)
906 {
907 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
908 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
909 struct regmap *regmap = spdif_priv->regmap;
910 u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET;
911
912 regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val);
913
914 return 0;
915 }
916
917 /* FSL SPDIF IEC958 controller defines */
918 static struct snd_kcontrol_new fsl_spdif_ctrls[] = {
919 /* Status cchanel controller */
920 {
921 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
922 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
923 .access = SNDRV_CTL_ELEM_ACCESS_READ |
924 SNDRV_CTL_ELEM_ACCESS_WRITE |
925 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
926 .info = fsl_spdif_info,
927 .get = fsl_spdif_pb_get,
928 .put = fsl_spdif_pb_put,
929 },
930 {
931 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
932 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
933 .access = SNDRV_CTL_ELEM_ACCESS_READ |
934 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
935 .info = fsl_spdif_info,
936 .get = fsl_spdif_capture_get,
937 },
938 /* User bits controller */
939 {
940 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
941 .name = "IEC958 Subcode Capture Default",
942 .access = SNDRV_CTL_ELEM_ACCESS_READ |
943 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
944 .info = fsl_spdif_info,
945 .get = fsl_spdif_subcode_get,
946 },
947 {
948 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
949 .name = "IEC958 Q-subcode Capture Default",
950 .access = SNDRV_CTL_ELEM_ACCESS_READ |
951 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
952 .info = fsl_spdif_qinfo,
953 .get = fsl_spdif_qget,
954 },
955 /* Valid bit error controller */
956 {
957 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
958 .name = "IEC958 V-Bit Errors",
959 .access = SNDRV_CTL_ELEM_ACCESS_READ |
960 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
961 .info = fsl_spdif_vbit_info,
962 .get = fsl_spdif_vbit_get,
963 },
964 /* DPLL lock info get controller */
965 {
966 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
967 .name = "RX Sample Rate",
968 .access = SNDRV_CTL_ELEM_ACCESS_READ |
969 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
970 .info = fsl_spdif_rxrate_info,
971 .get = fsl_spdif_rxrate_get,
972 },
973 /* User bit sync mode set/get controller */
974 {
975 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
976 .name = "IEC958 USyncMode CDText",
977 .access = SNDRV_CTL_ELEM_ACCESS_READ |
978 SNDRV_CTL_ELEM_ACCESS_WRITE |
979 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
980 .info = fsl_spdif_usync_info,
981 .get = fsl_spdif_usync_get,
982 .put = fsl_spdif_usync_put,
983 },
984 };
985
fsl_spdif_dai_probe(struct snd_soc_dai * dai)986 static int fsl_spdif_dai_probe(struct snd_soc_dai *dai)
987 {
988 struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai);
989
990 snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx,
991 &spdif_private->dma_params_rx);
992
993 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls));
994
995 return 0;
996 }
997
998 static struct snd_soc_dai_driver fsl_spdif_dai = {
999 .probe = &fsl_spdif_dai_probe,
1000 .playback = {
1001 .stream_name = "CPU-Playback",
1002 .channels_min = 2,
1003 .channels_max = 2,
1004 .rates = FSL_SPDIF_RATES_PLAYBACK,
1005 .formats = FSL_SPDIF_FORMATS_PLAYBACK,
1006 },
1007 .capture = {
1008 .stream_name = "CPU-Capture",
1009 .channels_min = 2,
1010 .channels_max = 2,
1011 .rates = FSL_SPDIF_RATES_CAPTURE,
1012 .formats = FSL_SPDIF_FORMATS_CAPTURE,
1013 },
1014 .ops = &fsl_spdif_dai_ops,
1015 };
1016
1017 static const struct snd_soc_component_driver fsl_spdif_component = {
1018 .name = "fsl-spdif",
1019 };
1020
1021 /* FSL SPDIF REGMAP */
1022 static const struct reg_default fsl_spdif_reg_defaults[] = {
1023 {REG_SPDIF_SCR, 0x00000400},
1024 {REG_SPDIF_SRCD, 0x00000000},
1025 {REG_SPDIF_SIE, 0x00000000},
1026 {REG_SPDIF_STL, 0x00000000},
1027 {REG_SPDIF_STR, 0x00000000},
1028 {REG_SPDIF_STCSCH, 0x00000000},
1029 {REG_SPDIF_STCSCL, 0x00000000},
1030 {REG_SPDIF_STC, 0x00020f00},
1031 };
1032
fsl_spdif_readable_reg(struct device * dev,unsigned int reg)1033 static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg)
1034 {
1035 switch (reg) {
1036 case REG_SPDIF_SCR:
1037 case REG_SPDIF_SRCD:
1038 case REG_SPDIF_SRPC:
1039 case REG_SPDIF_SIE:
1040 case REG_SPDIF_SIS:
1041 case REG_SPDIF_SRL:
1042 case REG_SPDIF_SRR:
1043 case REG_SPDIF_SRCSH:
1044 case REG_SPDIF_SRCSL:
1045 case REG_SPDIF_SRU:
1046 case REG_SPDIF_SRQ:
1047 case REG_SPDIF_STCSCH:
1048 case REG_SPDIF_STCSCL:
1049 case REG_SPDIF_SRFM:
1050 case REG_SPDIF_STC:
1051 return true;
1052 default:
1053 return false;
1054 }
1055 }
1056
fsl_spdif_volatile_reg(struct device * dev,unsigned int reg)1057 static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg)
1058 {
1059 switch (reg) {
1060 case REG_SPDIF_SRPC:
1061 case REG_SPDIF_SIS:
1062 case REG_SPDIF_SRL:
1063 case REG_SPDIF_SRR:
1064 case REG_SPDIF_SRCSH:
1065 case REG_SPDIF_SRCSL:
1066 case REG_SPDIF_SRU:
1067 case REG_SPDIF_SRQ:
1068 case REG_SPDIF_SRFM:
1069 return true;
1070 default:
1071 return false;
1072 }
1073 }
1074
fsl_spdif_writeable_reg(struct device * dev,unsigned int reg)1075 static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg)
1076 {
1077 switch (reg) {
1078 case REG_SPDIF_SCR:
1079 case REG_SPDIF_SRCD:
1080 case REG_SPDIF_SRPC:
1081 case REG_SPDIF_SIE:
1082 case REG_SPDIF_SIC:
1083 case REG_SPDIF_STL:
1084 case REG_SPDIF_STR:
1085 case REG_SPDIF_STCSCH:
1086 case REG_SPDIF_STCSCL:
1087 case REG_SPDIF_STC:
1088 return true;
1089 default:
1090 return false;
1091 }
1092 }
1093
1094 static const struct regmap_config fsl_spdif_regmap_config = {
1095 .reg_bits = 32,
1096 .reg_stride = 4,
1097 .val_bits = 32,
1098
1099 .max_register = REG_SPDIF_STC,
1100 .reg_defaults = fsl_spdif_reg_defaults,
1101 .num_reg_defaults = ARRAY_SIZE(fsl_spdif_reg_defaults),
1102 .readable_reg = fsl_spdif_readable_reg,
1103 .volatile_reg = fsl_spdif_volatile_reg,
1104 .writeable_reg = fsl_spdif_writeable_reg,
1105 .cache_type = REGCACHE_FLAT,
1106 };
1107
fsl_spdif_txclk_caldiv(struct fsl_spdif_priv * spdif_priv,struct clk * clk,u64 savesub,enum spdif_txrate index,bool round)1108 static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv,
1109 struct clk *clk, u64 savesub,
1110 enum spdif_txrate index, bool round)
1111 {
1112 static const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 };
1113 bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk);
1114 u64 rate_ideal, rate_actual, sub;
1115 u32 arate;
1116 u16 sysclk_dfmin, sysclk_dfmax, sysclk_df;
1117 u8 txclk_df;
1118
1119 /* The sysclk has an extra divisor [2, 512] */
1120 sysclk_dfmin = is_sysclk ? 2 : 1;
1121 sysclk_dfmax = is_sysclk ? 512 : 1;
1122
1123 for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) {
1124 for (txclk_df = 1; txclk_df <= 128; txclk_df++) {
1125 rate_ideal = rate[index] * txclk_df * 64ULL;
1126 if (round)
1127 rate_actual = clk_round_rate(clk, rate_ideal);
1128 else
1129 rate_actual = clk_get_rate(clk);
1130
1131 arate = rate_actual / 64;
1132 arate /= txclk_df * sysclk_df;
1133
1134 if (arate == rate[index]) {
1135 /* We are lucky */
1136 savesub = 0;
1137 spdif_priv->txclk_df[index] = txclk_df;
1138 spdif_priv->sysclk_df[index] = sysclk_df;
1139 spdif_priv->txrate[index] = arate;
1140 goto out;
1141 } else if (arate / rate[index] == 1) {
1142 /* A little bigger than expect */
1143 sub = (u64)(arate - rate[index]) * 100000;
1144 do_div(sub, rate[index]);
1145 if (sub >= savesub)
1146 continue;
1147 savesub = sub;
1148 spdif_priv->txclk_df[index] = txclk_df;
1149 spdif_priv->sysclk_df[index] = sysclk_df;
1150 spdif_priv->txrate[index] = arate;
1151 } else if (rate[index] / arate == 1) {
1152 /* A little smaller than expect */
1153 sub = (u64)(rate[index] - arate) * 100000;
1154 do_div(sub, rate[index]);
1155 if (sub >= savesub)
1156 continue;
1157 savesub = sub;
1158 spdif_priv->txclk_df[index] = txclk_df;
1159 spdif_priv->sysclk_df[index] = sysclk_df;
1160 spdif_priv->txrate[index] = arate;
1161 }
1162 }
1163 }
1164
1165 out:
1166 return savesub;
1167 }
1168
fsl_spdif_probe_txclk(struct fsl_spdif_priv * spdif_priv,enum spdif_txrate index)1169 static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv,
1170 enum spdif_txrate index)
1171 {
1172 static const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 };
1173 struct platform_device *pdev = spdif_priv->pdev;
1174 struct device *dev = &pdev->dev;
1175 u64 savesub = 100000, ret;
1176 struct clk *clk;
1177 char tmp[16];
1178 int i;
1179
1180 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
1181 sprintf(tmp, "rxtx%d", i);
1182 clk = devm_clk_get(&pdev->dev, tmp);
1183 if (IS_ERR(clk)) {
1184 dev_err(dev, "no rxtx%d clock in devicetree\n", i);
1185 return PTR_ERR(clk);
1186 }
1187 if (!clk_get_rate(clk))
1188 continue;
1189
1190 ret = fsl_spdif_txclk_caldiv(spdif_priv, clk, savesub, index,
1191 i == STC_TXCLK_SPDIF_ROOT);
1192 if (savesub == ret)
1193 continue;
1194
1195 savesub = ret;
1196 spdif_priv->txclk[index] = clk;
1197 spdif_priv->txclk_src[index] = i;
1198
1199 /* To quick catch a divisor, we allow a 0.1% deviation */
1200 if (savesub < 100)
1201 break;
1202 }
1203
1204 dev_dbg(&pdev->dev, "use rxtx%d as tx clock source for %dHz sample rate\n",
1205 spdif_priv->txclk_src[index], rate[index]);
1206 dev_dbg(&pdev->dev, "use txclk df %d for %dHz sample rate\n",
1207 spdif_priv->txclk_df[index], rate[index]);
1208 if (clk_is_match(spdif_priv->txclk[index], spdif_priv->sysclk))
1209 dev_dbg(&pdev->dev, "use sysclk df %d for %dHz sample rate\n",
1210 spdif_priv->sysclk_df[index], rate[index]);
1211 dev_dbg(&pdev->dev, "the best rate for %dHz sample rate is %dHz\n",
1212 rate[index], spdif_priv->txrate[index]);
1213
1214 return 0;
1215 }
1216
fsl_spdif_probe(struct platform_device * pdev)1217 static int fsl_spdif_probe(struct platform_device *pdev)
1218 {
1219 struct device_node *np = pdev->dev.of_node;
1220 struct fsl_spdif_priv *spdif_priv;
1221 struct spdif_mixer_control *ctrl;
1222 struct resource *res;
1223 void __iomem *regs;
1224 int irq, ret, i;
1225
1226 if (!np)
1227 return -ENODEV;
1228
1229 spdif_priv = devm_kzalloc(&pdev->dev, sizeof(*spdif_priv), GFP_KERNEL);
1230 if (!spdif_priv)
1231 return -ENOMEM;
1232
1233 spdif_priv->pdev = pdev;
1234
1235 /* Initialize this copy of the CPU DAI driver structure */
1236 memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai));
1237 spdif_priv->cpu_dai_drv.name = dev_name(&pdev->dev);
1238
1239 /* Get the addresses and IRQ */
1240 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1241 regs = devm_ioremap_resource(&pdev->dev, res);
1242 if (IS_ERR(regs))
1243 return PTR_ERR(regs);
1244
1245 spdif_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
1246 "core", regs, &fsl_spdif_regmap_config);
1247 if (IS_ERR(spdif_priv->regmap)) {
1248 dev_err(&pdev->dev, "regmap init failed\n");
1249 return PTR_ERR(spdif_priv->regmap);
1250 }
1251
1252 irq = platform_get_irq(pdev, 0);
1253 if (irq < 0)
1254 return irq;
1255
1256 ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0,
1257 dev_name(&pdev->dev), spdif_priv);
1258 if (ret) {
1259 dev_err(&pdev->dev, "could not claim irq %u\n", irq);
1260 return ret;
1261 }
1262
1263 /* Get system clock for rx clock rate calculation */
1264 spdif_priv->sysclk = devm_clk_get(&pdev->dev, "rxtx5");
1265 if (IS_ERR(spdif_priv->sysclk)) {
1266 dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n");
1267 return PTR_ERR(spdif_priv->sysclk);
1268 }
1269
1270 /* Get core clock for data register access via DMA */
1271 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core");
1272 if (IS_ERR(spdif_priv->coreclk)) {
1273 dev_err(&pdev->dev, "no core clock in devicetree\n");
1274 return PTR_ERR(spdif_priv->coreclk);
1275 }
1276
1277 spdif_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
1278 if (IS_ERR(spdif_priv->spbaclk))
1279 dev_warn(&pdev->dev, "no spba clock in devicetree\n");
1280
1281 /* Select clock source for rx/tx clock */
1282 spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1");
1283 if (IS_ERR(spdif_priv->rxclk)) {
1284 dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n");
1285 return PTR_ERR(spdif_priv->rxclk);
1286 }
1287 spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC;
1288
1289 for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
1290 ret = fsl_spdif_probe_txclk(spdif_priv, i);
1291 if (ret)
1292 return ret;
1293 }
1294
1295 /* Initial spinlock for control data */
1296 ctrl = &spdif_priv->fsl_spdif_control;
1297 spin_lock_init(&ctrl->ctl_lock);
1298
1299 /* Init tx channel status default value */
1300 ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT |
1301 IEC958_AES0_CON_EMPHASIS_5015;
1302 ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID;
1303 ctrl->ch_status[2] = 0x00;
1304 ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 |
1305 IEC958_AES3_CON_CLOCK_1000PPM;
1306
1307 spdif_priv->dpll_locked = false;
1308
1309 spdif_priv->dma_params_tx.maxburst = FSL_SPDIF_TXFIFO_WML;
1310 spdif_priv->dma_params_rx.maxburst = FSL_SPDIF_RXFIFO_WML;
1311 spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL;
1312 spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL;
1313
1314 /* Register with ASoC */
1315 dev_set_drvdata(&pdev->dev, spdif_priv);
1316
1317 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component,
1318 &spdif_priv->cpu_dai_drv, 1);
1319 if (ret) {
1320 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1321 return ret;
1322 }
1323
1324 ret = imx_pcm_dma_init(pdev, IMX_SPDIF_DMABUF_SIZE);
1325 if (ret && ret != -EPROBE_DEFER)
1326 dev_err(&pdev->dev, "imx_pcm_dma_init failed: %d\n", ret);
1327
1328 return ret;
1329 }
1330
1331 #ifdef CONFIG_PM_SLEEP
fsl_spdif_suspend(struct device * dev)1332 static int fsl_spdif_suspend(struct device *dev)
1333 {
1334 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev);
1335
1336 regmap_read(spdif_priv->regmap, REG_SPDIF_SRPC,
1337 &spdif_priv->regcache_srpc);
1338
1339 regcache_cache_only(spdif_priv->regmap, true);
1340 regcache_mark_dirty(spdif_priv->regmap);
1341
1342 return 0;
1343 }
1344
fsl_spdif_resume(struct device * dev)1345 static int fsl_spdif_resume(struct device *dev)
1346 {
1347 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev);
1348
1349 regcache_cache_only(spdif_priv->regmap, false);
1350
1351 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SRPC,
1352 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
1353 spdif_priv->regcache_srpc);
1354
1355 return regcache_sync(spdif_priv->regmap);
1356 }
1357 #endif /* CONFIG_PM_SLEEP */
1358
1359 static const struct dev_pm_ops fsl_spdif_pm = {
1360 SET_SYSTEM_SLEEP_PM_OPS(fsl_spdif_suspend, fsl_spdif_resume)
1361 };
1362
1363 static const struct of_device_id fsl_spdif_dt_ids[] = {
1364 { .compatible = "fsl,imx35-spdif", },
1365 { .compatible = "fsl,vf610-spdif", },
1366 {}
1367 };
1368 MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids);
1369
1370 static struct platform_driver fsl_spdif_driver = {
1371 .driver = {
1372 .name = "fsl-spdif-dai",
1373 .of_match_table = fsl_spdif_dt_ids,
1374 .pm = &fsl_spdif_pm,
1375 },
1376 .probe = fsl_spdif_probe,
1377 };
1378
1379 module_platform_driver(fsl_spdif_driver);
1380
1381 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1382 MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver");
1383 MODULE_LICENSE("GPL v2");
1384 MODULE_ALIAS("platform:fsl-spdif-dai");
1385