Lines Matching +full:non +full:- +full:compliant
3 CoreSight components are compliant with the ARM CoreSight architecture
11 * Required properties for all components *except* non-configurable replicators
12 and non-configurable funnels:
16 - Embedded Trace Buffer (version 1.0):
17 "arm,coresight-etb10", "arm,primecell";
19 - Trace Port Interface Unit:
20 "arm,coresight-tpiu", "arm,primecell";
22 - Trace Memory Controller, used for Embedded Trace Buffer(ETB),
26 "arm,coresight-tmc", "arm,primecell";
28 - Trace Programmable Funnel:
29 "arm,coresight-dynamic-funnel", "arm,primecell";
30 "arm,coresight-funnel", "arm,primecell"; (OBSOLETE. For
33 - Embedded Trace Macrocell (version 3.x) and
35 "arm,coresight-etm3x", "arm,primecell";
37 - Embedded Trace Macrocell (version 4.x), with memory mapped access.
38 "arm,coresight-etm4x", "arm,primecell";
40 - Embedded Trace Macrocell (version 4.x), with system register access only.
41 "arm,coresight-etm4x-sysreg";
43 - Coresight programmable Replicator :
44 "arm,coresight-dynamic-replicator", "arm,primecell";
46 - System Trace Macrocell:
47 "arm,coresight-stm", "arm,primecell"; [1]
48 - Coresight Address Translation Unit (CATU)
49 "arm,coresight-catu", "arm,primecell";
51 - Coresight Cross Trigger Interface (CTI):
52 "arm,coresight-cti", "arm,primecell";
53 See coresight-cti.yaml for full CTI definitions.
60 * clock-names: the name of the clocks referenced by the code.
79 * reg-names: the only acceptable values are "stm-base" and
80 "stm-stimulus-base", each corresponding to the areas defined in "reg".
83 See coresight-cti.yaml for full CTI definitions.
86 non-configurable replicators and non-configurable funnels:
90 - Coresight Non-configurable Replicator:
91 "arm,coresight-static-replicator";
92 "arm,coresight-replicator"; (OBSOLETE. For backward
95 - Coresight Non-configurable Funnel:
96 "arm,coresight-static-funnel";
102 * arm,coresight-loses-context-with-cpu : boolean. Indicates that the
112 registers via co-processor 14.
114 * qcom,skip-power-up: boolean. Indicates that an implementation can
123 * arm,buffer-size: size of contiguous buffer space for TMC ETR
127 * arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely
136 * qcom,replicator-loses-context: boolean. Indicates that the replicator
141 -------------------------------
150 * All output ports must be listed inside a child node named "out-ports"
151 * All input ports must be listed inside a child node named "in-ports".
158 compatible = "arm,coresight-etb10", "arm,primecell";
162 clock-names = "apb_pclk";
163 in-ports {
166 remote-endpoint = <&replicator_out_port0>;
173 compatible = "arm,coresight-tpiu", "arm,primecell";
177 clock-names = "apb_pclk";
178 in-ports {
181 remote-endpoint = <&replicator_out_port1>;
188 compatible = "arm,coresight-tmc", "arm,primecell";
192 clock-names = "apb_pclk";
193 in-ports {
196 remote-endpoint = <&replicator2_out_port0>;
201 out-ports {
204 remote-endpoint = <&catu_in_port>;
212 /* non-configurable replicators don't show up on the
215 compatible = "arm,coresight-static-replicator";
217 out-ports {
218 #address-cells = <1>;
219 #size-cells = <0>;
225 remote-endpoint = <&etb_in_port>;
232 remote-endpoint = <&tpiu_in_port>;
237 in-ports {
240 remote-endpoint = <&funnel_out_port0>;
248 * non-configurable funnel don't show up on the AMBA
251 compatible = "arm,coresight-static-funnel";
253 clock-names = "apb_pclk";
255 out-ports {
258 remote-endpoint = <&top_funnel_in>;
263 in-ports {
264 #address-cells = <1>;
265 #size-cells = <0>;
270 remote-endpoint = <&cluster0_etf_out>;
277 remote-endpoint = <&cluster1_etf_out>;
284 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
288 clock-names = "apb_pclk";
289 out-ports {
292 remote-endpoint =
298 in-ports {
299 #address-cells = <1>;
300 #size-cells = <0>;
305 remote-endpoint = <&ptm0_out_port>;
312 remote-endpoint = <&ptm1_out_port>;
319 remote-endpoint = <&etm0_out_port>;
328 compatible = "arm,coresight-etm3x", "arm,primecell";
333 clock-names = "apb_pclk";
334 out-ports {
337 remote-endpoint = <&funnel_in_port0>;
344 compatible = "arm,coresight-etm3x", "arm,primecell";
349 clock-names = "apb_pclk";
350 out-ports {
353 remote-endpoint = <&funnel_in_port1>;
361 compatible = "arm,coresight-stm", "arm,primecell";
364 reg-names = "stm-base", "stm-stimulus-base";
367 clock-names = "apb_pclk";
368 out-ports {
371 remote-endpoint = <&main_funnel_in_port2>;
380 compatible = "arm,coresight-catu", "arm,primecell";
384 clock-names = "apb_pclk";
387 in-ports {
390 remote-endpoint = <&etr_out_port>;