Lines Matching full:valid

9 data lines (16 bits), OE (output enable), ADV (address valid, used on some
36 in the hardware, or what valid values exist. The current hypothesis is that
80   CS or read followed by write on the same CS. Valid values 0 thru 15. Minimum
85   stays active for 1 extra cycle etc. Valid values 0 thru 15.
87   the first write to a page or burst memory. Valid values 0 thru 255.
89   first read to a page or burst memory. Valid values 0 thru 255.
91   cycle. Valid values 0 thru 15.
93   cycle. Valid values 0 thru 15.
100   assertion, with respect to the cycle where ADV (address valid) is asserted.
101   2 means 2 cycles between ADV and OE. Valid values 0, 1, 2 or 3.
104   assertion to OE assertion. Valid values 0 thru 15.