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3 The Exynos5433 clock controller generates and supplies clock to various
9 - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
12 - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF
14 - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF
15 which generates clocks for DRAM Memory Controller domain.
16 - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
18 - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
20 - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS
22 - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D
24 - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP
26 - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD
29 and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS
31 - "samsung,exynos5433-cmu-g3d" - clock controller compatible for CMU_G3D
33 - "samsung,exynos5433-cmu-gscl" - clock controller compatible for CMU_GSCL
35 - "samsung,exynos5433-cmu-apollo"- clock controller compatible for CMU_APOLLO
37 - "samsung,exynos5433-cmu-atlas" - clock controller compatible for CMU_ATLAS
39 L2 cache controller.
40 - "samsung,exynos5433-cmu-mscl" - clock controller compatible for CMU_MSCL
42 - "samsung,exynos5433-cmu-mfc" - clock controller compatible for CMU_MFC
44 - "samsung,exynos5433-cmu-hevc" - clock controller compatible for CMU_HEVC
46 - "samsung,exynos5433-cmu-isp" - clock controller compatible for CMU_ISP
48 - "samsung,exynos5433-cmu-cam0" - clock controller compatible for CMU_CAM0
51 - "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1
53 - "samsung,exynos5433-cmu-imem" - clock controller compatible for CMU_IMEM
56 - reg: physical base address of the controller and length of memory mapped
61 - clocks: list of the clock controller input clock identifiers,
63 to find the input clocks for a given controller.
65 - clock-names: list of the clock controller input clock names,
68 Input clocks for top clock controller:
74 Input clocks for cpif clock controller:
77 Input clocks for mif clock controller:
81 Input clocks for fsys clock controller:
93 Input clocks for g2d clock controller:
98 Input clocks for disp clock controller:
109 Input clocks for audio clock controller:
113 Input clocks for bus0 clock controller:
116 Input clocks for bus1 clock controller:
119 Input clocks for bus2 clock controller:
123 Input clocks for g3d clock controller:
127 Input clocks for gscl clock controller:
132 Input clocks for apollo clock controller:
136 Input clocks for atlas clock controller:
140 Input clocks for mscl clock controller:
145 Input clocks for mfc clock controller:
149 Input clocks for hevc clock controller:
153 Input clocks for isp clock controller:
158 Input clocks for cam0 clock controller:
164 Input clocks for cam1 clock controller:
173 Input clocks for imem clock controller:
199 Example 2: Examples of clock controller nodes are listed below.
201 cmu_top: clock-controller@10030000 {
216 cmu_cpif: clock-controller@10fc0000 {
225 cmu_mif: clock-controller@105b0000 {
236 cmu_peric: clock-controller@14c80000 {
242 cmu_peris: clock-controller@10040000 {
248 cmu_fsys: clock-controller@156e0000 {
275 cmu_g2d: clock-controller@12460000 {
289 cmu_disp: clock-controller@13b90000 {
315 cmu_aud: clock-controller@114c0000 {
325 cmu_bus0: clock-controller@13600000 {
334 cmu_bus1: clock-controller@14800000 {
343 cmu_bus2: clock-controller@13400000 {
352 cmu_g3d: clock-controller@14aa0000 {
362 cmu_gscl: clock-controller@13cf0000 {
376 cmu_apollo: clock-controller@11900000 {
385 cmu_atlas: clock-controller@11800000 {
394 cmu_mscl: clock-controller@105d0000 {
408 cmu_mfc: clock-controller@15280000 {
418 cmu_hevc: clock-controller@14f80000 {
428 cmu_isp: clock-controller@146d0000 {
442 cmu_cam0: clock-controller@120d0000 {
458 cmu_cam1: clock-controller@145d0000 {
480 cmu_imem: clock-controller@11060000 {
495 Example 3: UART controller node that consumes the clock generated by the clock
496 controller.