Lines Matching full:clock

1 * Samsung Exynos7 Clock Controller
3 Exynos7 clock controller has various blocks which are instantiated
4 independently from the device-tree. These clock controllers
8 Each clock is assigned an identifier and client nodes can use
9 this identifier to specify the clock which they consume. All
11 dt-bindings/clock/exynos7-clk.h header and can be used in
17 is expected that they are defined using standard clock bindings
18 with following clock-output-names:
20  - "fin_pll" - PLL input clock from XXTI
22 Required Properties for Clock Controller:
24  - compatible: clock controllers will use one of the following
25 	compatible strings to indicate the clock controller
28 	- "samsung,exynos7-clock-topc"
29 	- "samsung,exynos7-clock-top0"
30 	- "samsung,exynos7-clock-top1"
31 	- "samsung,exynos7-clock-ccore"
32 	- "samsung,exynos7-clock-peric0"
33 	- "samsung,exynos7-clock-peric1"
34 	- "samsung,exynos7-clock-peris"
35 	- "samsung,exynos7-clock-fsys0"
36 	- "samsung,exynos7-clock-fsys1"
37 	- "samsung,exynos7-clock-mscl"
38 	- "samsung,exynos7-clock-aud"
43  - #clock-cells: should be 1.
45  - clocks: list of clock identifiers which are fed as the input to
46 	the given clock controller. Please refer the next section to
49 - clock-names: list of names of clocks which are fed as the input
50 	to the given clock controller.
52 Input clocks for top0 clock controller:
60 Input clocks for top1 clock controller:
67 Input clocks for ccore clock controller:
71 Input clocks for peric0 clock controller:
76 Input clocks for peric1 clock controller:
91 Input clocks for peris clock controller:
95 Input clocks for fsys0 clock controller:
100 Input clocks for fsys1 clock controller:
106 Input clocks for aud clock controller: