Lines Matching full:clock

4 $id: http://devicetree.org/schemas/clock/imx7ulp-pcc-clock.yaml#
7 title: Clock bindings for Freescale i.MX7ULP Peripheral Clock Control (PCC) modules
13   i.MX7ULP Clock functions are under joint control of the System
14   Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
18   and A7 domain. Except for a few clock sources shared between two
19   domains, such as the System Oscillator clock, the Slow IRC (SIRC),
20   and and the Fast IRC clock (FIRCLK), clock sources and clock
23   M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
24   A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
26   Note: this binding doc is only for A7 clock domain.
28   The Peripheral Clock Control (PCC) is responsible for clock selection,
29   optional division and clock gating mode for peripherals in their
32   The clock consumer should specify the desired clock by having the clock
34   See include/dt-bindings/clock/imx7ulp-clock.h for the full list of
35   i.MX7ULP clock IDs of each module.
46   '#clock-cells':
51       - description: nic1 bus clock
52       - description: nic1 clock
53       - description: ddr clock
58       - description: system osc bus clock
59       - description: fast internal reference clock bus
61       - description: system pll bus clock
63   clock-names:
80   - '#clock-cells'
82   - clock-names
88     #include <dt-bindings/clock/imx7ulp-clock.h>
91     clock-controller@403f0000 {
94         #clock-cells = <1>;
106          clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
119         clock-names ="ipg", "ahb", "per";