Lines Matching +full:fixed +full:- +full:clock

1 Status: Unstable - ABI compatibility may be broken in the future
9 This binding uses the common clock binding[1].
11 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
14 - #clock-cells : from common clock binding; shall be set to 0.
15 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
16 - clocks : parent clock phandle
17 - reg - pll control0 and pll multipler registers
18 - reg-names : control, multiplier and post-divider. The multiplier and
19 		post-divider registers are applicable only for main pll clock
20 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
25 		#clock-cells = <0>;
26 		compatible = "ti,keystone,main-pll-clock";
29 		reg-names = "control", "multiplier", "post-divider";
30 		fixed-postdiv = <2>;
34 		#clock-cells = <0>;
35 		compatible = "ti,keystone,pll-clock";
37 		clock-output-names = "pa-pll-clk";
39 		reg-names = "control";
43 - #clock-cells : from common clock binding; shall be set to 0.
44 - compatible : shall be "ti,keystone,pll-mux-clock"
45 - clocks : link phandles of parent clocks
46 - reg - pll mux register
47 - bit-shift : number of bits to shift the bit-mask
48 - bit-mask : arbitrary bitmask for programming the mux
51 - clock-output-names : From common clock binding.
55 		#clock-cells = <0>;
56 		compatible = "ti,keystone,pll-mux-clock";
59 		bit-shift = <23>;
60 		bit-mask = <1>;
61 		clock-output-names = "mainmuxclk";
65 - #clock-cells : from common clock binding; shall be set to 0.
66 - compatible : shall be "ti,keystone,pll-divider-clock"
67 - clocks : parent clock phandle
68 - reg - pll mux register
69 - bit-shift : number of bits to shift the bit-mask
70 - bit-mask : arbitrary bitmask for programming the divider
73 - clock-output-names : From common clock binding.
77 		#clock-cells = <0>;
78 		compatible = "ti,keystone,pll-divider-clock";
81 		bit-shift = <0>;
82 		bit-mask = <8>;
83 		clock-output-names = "gemtraceclk";