Lines Matching +full:dw +full:- +full:apb +full:- +full:uart

5   - compatible: Must be:
6     - "renesas,r9a06g032-sysctrl"
7   - reg: Base address and length of the SYSCTRL IO block.
8   - #clock-cells: Must be 1
9   - clocks: References to the parent clocks:
10 	- external 40mhz crystal.
11 	- external (optional) 32.768khz
12 	- external (optional) jtag input
13 	- external (optional) RGMII_REFCLK
14   - clock-names: Must be:
15         clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
16   - #power-domain-cells: Must be 0
19 --------
21   - SYSCTRL node:
23 	sysctrl: system-controller@4000c000 {
24 		compatible = "renesas,r9a06g032-sysctrl";
26 		#clock-cells = <1>;
30 		clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
31 		#power-domain-cells = <0>;
34   - Other nodes can use the clocks provided by SYSCTRL as in:
36 	#include <dt-bindings/clock/r9a06g032-sysctrl.h>
38 		compatible = "snps,dw-apb-uart";
41 		reg-shift = <2>;
42 		reg-io-width = <4>;
44 		clock-names = "baudclk", "apb_pclk";
45 		power-domains = <&sysctrl>;