Lines Matching +full:dw +full:- +full:apb +full:- +full:uart
9 - compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or
10 "rockchip,rk3066a-cru"
11 - reg: physical base address of the controller and length of memory mapped
13 - #clock-cells: should be 1.
14 - #reset-cells: should be 1.
18 - rockchip,grf: phandle to the syscon managing the "general register files"
23 preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
24 dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
31 clock-output-names:
32 - "xin24m" - crystal input - required,
33 - "xin32k" - rtc clock - optional,
34 - "xin27m" - 27mhz crystal input on rk3066 - optional,
35 - "ext_hsadc" - external HSADC clock - optional,
36 - "ext_cif0" - external camera clock - optional,
37 - "ext_rmii" - external RMII clock - optional,
38 - "ext_jtag" - externalJTAG clock - optional
43 compatible = "rockchip,rk3188-cru";
47 #clock-cells = <1>;
48 #reset-cells = <1>;
51 Example: UART controller node that consumes the clock generated by the clock
55 compatible = "snps,dw-apb-uart";
58 reg-shift = <2>;
59 reg-io-width = <1>;