Lines Matching full:output
12 The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output
43 The second value is the output or synthesizer index.
54 feedback divider. Must be such that the PLL output is in the valid range. For
61 temporarily stop all output clocks, don't do this if the chip is generating
70 The child nodes list the output clocks.
73 If a child node for a clock output is not set, the configuration remains
77 - reg: number of clock output.
80 - vdd-supply: Regulator node for VDD for this output. The driver selects default
82 - silabs,format: Output format, one of:
86 - silabs,common-mode: Manually override output common mode, see [2] for values
87 - silabs,amplitude: Manually override output amplitude, see [2] for values
88 - silabs,synth-master: boolean. If present, this output is allowed to change the
90 - silabs,silabs,disable-high: boolean. If set, the clock output is driven HIGH
126 * Output 6 configuration:
137 * Output 8 configuration:
152 clocks = <&si5341 0 7>; /* Output 7 */
154 /* Set output 7 to use syntesizer 3 as its parent */
157 /* Set output 7 to 148.5 MHz using a synth frequency of 594 MHz */
165 * since output 0 is a synth-master, the synth will be automatically set
167 * frequency. We give control over synth 2 to this output here.