Lines Matching +full:32 +full:- +full:bit

6 Please refer to clock-bindings.txt for common clock controller binding usage.
10 - compatible: Should be:
11   "st,stm32f42xx-rcc"
12   "st,stm32f469-rcc"
13   "st,stm32f746-rcc"
14   "st,stm32f769-rcc"
16 - reg: should be register base and length as documented in the
18 - #reset-cells: 1, see below
19 - #clock-cells: 2, device nodes should specify the clock in their "clocks"
23 - clocks: External oscillator clock phandle
24   - high speed external clock signal (HSE)
25   - external I2S clock (I2S_CKIN)
30 		#reset-cells = <1>;
31 		#clock-cells = <2>
32 		compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
42 The secondary index is the bit number within the RCC register bank, starting
45 It is calculated as: index = register_offset / 4 * 32 + bit_offset.
46 Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31).
48 To simplify the usage and to share bit definition with the reset and clock
50 human-readble format.
53  - include/dt-bindings/mfd/stm32f4-rcc.h
57 	/* Gated clock, AHB1 bit 0 (GPIOA) */
62 	/* Gated clock, AHB2 bit 4 (CRYP) */
76 	2	CLK_LSI		(low-power clock source)
77 	3	CLK_LSE		(generated from a 32.768 kHz low-speed external
80 	5	CLK_RTC		(real-time clock)
83 	8	CLK_LCD		(LCD-TFT)
92 	16	CLK_HDMI_CEC	(HDMI-CEC clock)
93 	17	CLK_SPDIF	(SPDIF-Rx clock)
108 	32	CLK_DFSDM1
127 The index is the bit number within the RCC registers bank, starting from RCC
129 It is calculated as: index = register_offset / 4 * 32 + bit_offset.
130 Where bit_offset is the bit offset within the register.
132   crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140