Lines Matching full:clock

4 registers call CFGCHIPn. Some of these registers function as clock
7 All of the clock nodes described below must be child nodes of a CFGCHIP node
14 - #clock-cells: from common clock binding; shall be set to 1.
15 - clocks: phandles to the parent clocks corresponding to clock-names
16 - clock-names: shall be "fck", "usb_refclkin", "auxclk"
18 This node provides two clocks. The clock at index 0 is the USB 2.0 PHY 48MHz
19 clock and the clock at index 1 is the USB 1.1 PHY 48MHz clock.
21 eHRPWM Time Base Clock (TBCLK)
25 - #clock-cells: from common clock binding; shall be set to 0.
26 - clocks: phandle to the parent clock
27 - clock-names: shall be "fck"
33 - #clock-cells: from common clock binding; shall be set to 0.
34 - clocks: phandle to the parent clock
35 - clock-names: shall be "pll0_pllout"
37 EMIFA clock source (ASYNC1)
41 - #clock-cells: from common clock binding; shall be set to 0.
42 - clocks: phandles to the parent clocks corresponding to clock-names
43 - clock-names: shall be "pll0_sysclk3", "div4.5"
45 ASYNC3 clock source
49 - #clock-cells: from common clock binding; shall be set to 0.
50 - clocks: phandles to the parent clocks corresponding to clock-names
51 - clock-names: shall be "pll0_sysclk2", "pll1_sysclk2"
61 			#clock-cells = <1>;
63 			clock-names = "fck", "usb_refclkin", "auxclk";
67 			#clock-cells = <0>;
69 			clock-names = "fck";
73 			#clock-cells = <0>;
75 			clock-names = "pll0_pllout";
79 			#clock-cells = <0>;
81 			clock-names = "pll0_sysclk3", "div4.5";
85 			#clock-cells = <0>;
87 			clock-names = "pll0_sysclk2", "pll1_sysclk2";
92 - Documentation/devicetree/bindings/clock/clock-bindings.txt