Lines Matching +full:cortex +full:- +full:a7
5 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
6 - clock-names: Should contain the following:
7 "cpu" - The multiplexer for clock input of CPU cluster.
8 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
11 Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
13 - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp.txt
15 - proc-supply: Regulator for Vproc of CPU cluster.
18 - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
23 - #cooling-cells:
25 Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
30 compatible = "operating-points-v2";
31 opp-shared;
33 opp-598000000 {
34 opp-hz = /bits/ 64 <598000000>;
35 opp-microvolt = <1050000>;
38 opp-747500000 {
39 opp-hz = /bits/ 64 <747500000>;
40 opp-microvolt = <1050000>;
43 opp-1040000000 {
44 opp-hz = /bits/ 64 <1040000000>;
45 opp-microvolt = <1150000>;
48 opp-1196000000 {
49 opp-hz = /bits/ 64 <1196000000>;
50 opp-microvolt = <1200000>;
53 opp-1300000000 {
54 opp-hz = /bits/ 64 <1300000000>;
55 opp-microvolt = <1300000>;
61 compatible = "arm,cortex-a7";
65 clock-names = "cpu", "intermediate";
66 operating-points-v2 = <&cpu_opp_table>;
67 #cooling-cells = <2>;
71 compatible = "arm,cortex-a7";
73 operating-points-v2 = <&cpu_opp_table>;
77 compatible = "arm,cortex-a7";
79 operating-points-v2 = <&cpu_opp_table>;
83 compatible = "arm,cortex-a7";
85 operating-points-v2 = <&cpu_opp_table>;
90 compatible = "operating-points-v2";
91 opp-shared;
93 opp-507000000 {
94 opp-hz = /bits/ 64 <507000000>;
95 opp-microvolt = <859000>;
98 opp-702000000 {
99 opp-hz = /bits/ 64 <702000000>;
100 opp-microvolt = <908000>;
103 opp-1001000000 {
104 opp-hz = /bits/ 64 <1001000000>;
105 opp-microvolt = <983000>;
108 opp-1105000000 {
109 opp-hz = /bits/ 64 <1105000000>;
110 opp-microvolt = <1009000>;
113 opp-1183000000 {
114 opp-hz = /bits/ 64 <1183000000>;
115 opp-microvolt = <1028000>;
118 opp-1404000000 {
119 opp-hz = /bits/ 64 <1404000000>;
120 opp-microvolt = <1083000>;
123 opp-1508000000 {
124 opp-hz = /bits/ 64 <1508000000>;
125 opp-microvolt = <1109000>;
128 opp-1573000000 {
129 opp-hz = /bits/ 64 <1573000000>;
130 opp-microvolt = <1125000>;
135 compatible = "operating-points-v2";
136 opp-shared;
138 opp-507000000 {
139 opp-hz = /bits/ 64 <507000000>;
140 opp-microvolt = <828000>;
143 opp-702000000 {
144 opp-hz = /bits/ 64 <702000000>;
145 opp-microvolt = <867000>;
148 opp-1001000000 {
149 opp-hz = /bits/ 64 <1001000000>;
150 opp-microvolt = <927000>;
153 opp-1209000000 {
154 opp-hz = /bits/ 64 <1209000000>;
155 opp-microvolt = <968000>;
158 opp-1404000000 {
159 opp-hz = /bits/ 64 <1007000000>;
160 opp-microvolt = <1028000>;
163 opp-1612000000 {
164 opp-hz = /bits/ 64 <1612000000>;
165 opp-microvolt = <1049000>;
168 opp-1807000000 {
169 opp-hz = /bits/ 64 <1807000000>;
170 opp-microvolt = <1089000>;
173 opp-1989000000 {
174 opp-hz = /bits/ 64 <1989000000>;
175 opp-microvolt = <1125000>;
181 compatible = "arm,cortex-a53";
183 enable-method = "psci";
184 cpu-idle-states = <&CPU_SLEEP_0>;
187 clock-names = "cpu", "intermediate";
188 operating-points-v2 = <&cpu_opp_table_a>;
193 compatible = "arm,cortex-a53";
195 enable-method = "psci";
196 cpu-idle-states = <&CPU_SLEEP_0>;
199 clock-names = "cpu", "intermediate";
200 operating-points-v2 = <&cpu_opp_table_a>;
205 compatible = "arm,cortex-a57";
207 enable-method = "psci";
208 cpu-idle-states = <&CPU_SLEEP_0>;
211 clock-names = "cpu", "intermediate";
212 operating-points-v2 = <&cpu_opp_table_b>;
217 compatible = "arm,cortex-a57";
219 enable-method = "psci";
220 cpu-idle-states = <&CPU_SLEEP_0>;
223 clock-names = "cpu", "intermediate";
224 operating-points-v2 = <&cpu_opp_table_b>;
228 proc-supply = <&mt6397_vpca15_reg>;
232 proc-supply = <&mt6397_vpca15_reg>;
236 proc-supply = <&da9211_vcpu_reg>;
237 sram-supply = <&mt6397_vsramca7_reg>;
241 proc-supply = <&da9211_vcpu_reg>;
242 sram-supply = <&mt6397_vsramca7_reg>;