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1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 DMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a four-cell specifier for each
19 -bit 9: Peripheral Increment Address
20 0x0: no address increment between transfers
21 0x1: increment address between transfers
22 -bit 10: Memory Increment Address
23 0x0: no address increment between transfers
24 0x1: increment address between transfers
25 -bit 15: Peripheral Increment Offset Size
27 0x1: offset size is fixed to 4 (32-bit alignment)
28 -bit 16-17: Priority level
34 -bit 0-1: DMA FIFO threshold selection
39 -bit 2: DMA direct mode
40 0x0: FIFO mode with threshold selectable with bit 0-1
46 - Amelie Delaunay <amelie.delaunay@st.com>
49 - $ref: "dma-controller.yaml#"
52 "#dma-cells":
56 const: st,stm32-dma
66 description: Should contain all of the per-channel DMA
67 interrupts in ascending order with respect to the
76 supports memory-to-memory transfer
79 - compatible
80 - reg
81 - clocks
82 - interrupts
87 - |
88 #include <dt-bindings/interrupt-controller/arm-gic.h>
89 #include <dt-bindings/clock/stm32mp1-clks.h>
90 #include <dt-bindings/reset/stm32mp1-resets.h>
91 dma-controller@40026400 {
92 compatible = "st,stm32-dma";
103 #dma-cells = <4>;
106 dma-requests = <8>;