Lines Matching +full:dma +full:- +full:coherent

1 Xilinx ZynqMP DMA engine, it does support memory to memory transfers,
3 control and rate control support for slave/peripheral dma access.
6 - compatible		: Should be "xlnx,zynqmp-dma-1.0"
7 - reg			: Memory map for gdma/adma module access.
8 - interrupts		: Should contain DMA channel interrupt.
9 - xlnx,bus-width	: Axi buswidth in bits. Should contain 128 or 64
10 - clock-names		: List of input clocks "clk_main", "clk_apb"
14 - dma-coherent		: Present if dma operations are coherent.
18 fpd_dma_chan1: dma@fd500000 {
19 	compatible = "xlnx,zynqmp-dma-1.0";
21 	interrupt-parent = <&gic>;
23 	clock-names = "clk_main", "clk_apb";
24 	xlnx,bus-width = <128>;
25 	dma-coherent;