Lines Matching +full:reg +full:- +full:shift

1 Device tree configuration for i2c-ocores
4 - compatible      : "opencores,i2c-ocores"
6                     "sifive,fu540-c000-i2c", "sifive,i2c0"
8                     FU540-C000 SoC. Please refer to sifive-blocks-ip-versioning.txt
10 - reg             : bus address start and address range size of device
11 - clocks          : handle to the controller clock; see the note below.
12                     Mutually exclusive with opencores,ip-clock-frequency
13 - opencores,ip-clock-frequency: frequency of the controller clock in Hz;
15 - #address-cells  : should be <1>
16 - #size-cells     : should be <0>
19 - interrupts      : interrupt number.
20 - clock-frequency : frequency of bus clock in Hz; see the note below.
22 - reg-shift       : device register offsets are shifted by this value
23 - reg-io-width    : io register width in bytes (1, 2 or 4)
24 - regstep         : deprecated, use reg-shift above
27 clock-frequency property is meant to control the bus frequency for i2c bus
30 - if clock-frequency is present and neither opencores,ip-clock-frequency nor
31   clocks are, then clock-frequency specifies i2c controller clock frequency.
34 - if clocks is present it specifies i2c controller clock. clock-frequency
36 - if opencores,ip-clock-frequency is present it specifies i2c controller
37   clock frequency. clock-frequency property specifies i2c bus frequency.
42 		#address-cells = <1>;
43 		#size-cells = <0>;
44 		compatible = "opencores,i2c-ocores";
45 		reg = <0xa0000000 0x8>;
47 		opencores,ip-clock-frequency = <20000000>;
49 		reg-shift = <0>;	/* 8 bit registers */
50 		reg-io-width = <1>;	/* 8 bit read/write */
54 			reg = <0x60>;
59 		#address-cells = <1>;
60 		#size-cells = <0>;
61 		compatible = "opencores,i2c-ocores";
62 		reg = <0xa0000000 0x8>;
65 		clock-frequency = <400000>; /* i2c bus frequency 400 KHz */
67 		reg-shift = <0>;	/* 8 bit registers */
68 		reg-io-width = <1>;	/* 8 bit read/write */
72 			reg = <0x60>;