Lines Matching +full:non +full:- +full:secure
1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
31 - const: qcom,smmu-v2
33 - description: Qcom SoCs implementing "arm,mmu-500"
35 - enum:
36 - qcom,sc7180-smmu-500
37 - qcom,sdm845-smmu-500
38 - qcom,sm8150-smmu-500
39 - qcom,sm8250-smmu-500
40 - const: arm,mmu-500
41 - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
43 - enum:
44 - qcom,sc7180-smmu-v2
45 - qcom,sdm845-smmu-v2
46 - const: qcom,adreno-smmu
47 - const: qcom,smmu-v2
48 - description: Marvell SoCs implementing "arm,mmu-500"
50 - const: marvell,ap806-smmu-500
51 - const: arm,mmu-500
52 - description: NVIDIA SoCs that program two ARM MMU-500s identically
54 - enum:
55 - nvidia,tegra194-smmu
56 - const: nvidia,smmu-500
57 - items:
58 - const: arm,mmu-500
59 - const: arm,smmu-v2
60 - items:
61 - enum:
62 - arm,mmu-400
63 - arm,mmu-401
64 - const: arm,smmu-v1
65 - enum:
66 - arm,smmu-v1
67 - arm,smmu-v2
68 - arm,mmu-400
69 - arm,mmu-401
70 - arm,mmu-500
71 - cavium,smmu-v2
77 '#global-interrupts':
81 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters
83 '#iommu-cells':
99 Interrupt list, with the first #global-interrupts entries corresponding to
107 dma-coherent:
115 calxeda,smmu-secure-config-access:
118 Enable proper handling of buggy implementations that always use secure
119 access to SMMU configuration registers. In this case non-secure aliases of
120 secure registers have to be used during SMMU configuration.
122 stream-match-mask:
125 For SMMUs supporting stream matching and using #iommu-cells = <1>,
129 Stream ID (e.g. for certain MMU-500 configurations given globally unique
131 using stream matching with #iommu-cells = <2>, and may be ignored if
134 clock-names:
136 - const: bus
137 - const: iface
141 - description: bus clock required for downstream bus access and for the
143 - description: interface clock required to access smmu's registers
146 power-domains:
150 - compatible
151 - reg
152 - '#global-interrupts'
153 - '#iommu-cells'
154 - interrupts
159 - if:
164 - nvidia,tegra194-smmu
176 - |+
179 compatible = "arm,smmu-v1";
181 #global-interrupts = <2>;
188 #iommu-cells = <1>;
200 compatible = "arm,smmu-v1";
202 #global-interrupts = <2>;
209 #iommu-cells = <2>;
224 /* ARM MMU-500 with 10-bit stream ID input configuration */
226 compatible = "arm,mmu-500", "arm,smmu-v2";
228 #global-interrupts = <2>;
235 #iommu-cells = <1>;
236 /* always ignore appended 5-bit TBU number */
237 stream-match-mask = <0x7c00>;
241 /* bus whose child devices emit one unique 10-bit stream
243 iommu-map = <0 &smmu3 0 0x400>;
248 - |+
249 /* Qcom's arm,smmu-v2 implementation */
250 #include <dt-bindings/interrupt-controller/arm-gic.h>
251 #include <dt-bindings/interrupt-controller/irq.h>
253 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
256 #global-interrupts = <1>;
260 #iommu-cells = <1>;
261 power-domains = <&mmcc 0>;
265 clock-names = "bus", "iface";