Lines Matching full:input

32   # PHY DLL input delays:
37   cdns,phy-input-delay-sd-highspeed:
38     description: Value of the delay in the input path for SD high-speed timing
43   cdns,phy-input-delay-legacy:
44     description: Value of the delay in the input path for legacy timing
49   cdns,phy-input-delay-sd-uhs-sdr12:
50     description: Value of the delay in the input path for SD UHS SDR12 timing
55   cdns,phy-input-delay-sd-uhs-sdr25:
56     description: Value of the delay in the input path for SD UHS SDR25 timing
61   cdns,phy-input-delay-sd-uhs-sdr50:
62     description: Value of the delay in the input path for SD UHS SDR50 timing
67   cdns,phy-input-delay-sd-uhs-ddr50:
68     description: Value of the delay in the input path for SD UHS DDR50 timing
73   cdns,phy-input-delay-mmc-highspeed:
74     description: Value of the delay in the input path for MMC high-speed timing
79   cdns,phy-input-delay-mmc-ddr:
80     description: Value of the delay in the input path for eMMC high-speed DDR timing
108       Value of the delay introduced on the dat_strobe input used in