Lines Matching full:nand

1 * Broadcom STB NAND Controller
3 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
19                      the core NAND controller, of the following form:
35 - reg              : the register start and length for NAND register region.
37                      (optional) NAND flash cache range (if at non-standard offset)
39                      ranges. Should contain "nand" and (optionally)
40                      "flash-dma" or "flash-edu" and/or "nand-cache".
41 - interrupts       : The NAND CTLRDY interrupt, (if Flash DMA is available)
45                      May be "nand", if the SoC has the individual NAND
52 - clock                     : reference to the clock for the NAND controller
53 - clock-names               : "nand" (required for the above clock)
54 - brcm,nand-has-wp          : Some versions of this IP include a write-protect
59  -- Additional SoC-specific NAND controller properties --
61 The NAND controller is integrated differently on the variety of SoCs on which it
63 with which to control the 8 exposed NAND interrupts, as well as hardware for
67 ways, sometimes with registers that lump multiple NAND-related functions
70 we define additional 'compatible' properties and associated register resources within the NAND cont…
76    * "brcm,nand-bcm63138"
79      - reg-names: (required) "nand-int-base"
81    * "brcm,nand-bcm6368"
82      - compatible: should contain "brcm,nand-bcm<soc>", "brcm,nand-bcm6368"
85      - reg-names: (required) "nand-int-base"
87    * "brcm,nand-iproc"
95 * NAND chip-select
98 to represent enabled chip-selects which (may) contain NAND flash chips. Their
109 - nand-ecc-strength         : see nand-controller.yaml
110 - nand-ecc-step-size        : must be 512 or 1024. See nand-controller.yaml
111 - nand-on-flash-bbt         : boolean, to enable the on-flash BBT for this
112                               chip-select. See nand-controller.yaml
113 - brcm,nand-oob-sector-size : integer, to denote the spare area sector size
119                               the flash geometry (particularly the NAND page
121                               from NAND, the boot controller has only a limited
131 nand@f0442800 {
135 	reg-names = "nand", "flash-dma";
145 		nand-on-flash-bbt;
146 		nand-ecc-strength = <12>;
147 		nand-ecc-step-size = <512>;
164 nand@10000200 {
165 	compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368",
170 	reg-names = "nand", "nand-cache", "nand-int-base";
174 	clock-names = "nand";
182 		nand-on-flash-bbt;
183 		nand-ecc-strength = <1>;
184 		nand-ecc-step-size = <512>;