Lines Matching full:ecc

19   The ECC strength and ECC step size properties define the user
21   they request the ECC engine to correct {strength} bit errors per
49       nand-ecc-mode:
51           Desired ECC engine, either hardware (most of the time
54           and should be replaced by soft and nand-ecc-algo.
58       nand-ecc-engine:
62           A phandle on the hardware ECC engine if any. There are
64           1/ The ECC engine is part of the NAND controller, in this
66           2/ The ECC engine is part of the NAND part (on-die), in this
68           3/ The ECC engine is external, in this case the phandle should
69           reference the specific ECC engine node.
71       nand-use-soft-ecc-engine:
73         description: Use a software ECC engine.
75       nand-no-ecc-engine:
77         description: Do not use any ECC correction.
79       nand-ecc-placement:
84           Location of the ECC bytes. This location is unknown by default
85           but can be explicitly set to "oob", if all ECC bytes are
86           known to be stored in the OOB area, or "interleaved" if ECC
89       nand-ecc-algo:
91           Desired ECC algorithm.
113       nand-ecc-strength:
115           Maximum number of bits that can be corrected per ECC step.
119       nand-ecc-step-size:
121           Number of data bytes covered by a single ECC step.
125       nand-ecc-maximize:
128           Whether or not the ECC strength should be maximized. The
129           maximum ECC strength is both controller and chip
130           dependent. The ECC engine has to select the ECC config
140           use this information to select ECC algorithms supported by
174         nand-ecc-mode = "soft";
175         nand-ecc-algo = "bch";