Lines Matching +full:nand +full:- +full:ecc +full:- +full:mode
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NAND Chip and NAND Controller Generic Binding
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
14 The NAND controller should be represented with its own DT node, and
15 all NAND chips attached to this controller should be defined as
16 children nodes of the NAND controller. This representation should be
19 The ECC strength and ECC step size properties define the user
21 they request the ECC engine to correct {strength} bit errors per
24 The interpretation of these parameters is implementation-defined, so
31 pattern: "^nand-controller(@.*)?"
33 "#address-cells":
36 "#size-cells":
42 "^nand@[a-f0-9]$":
47 Contains the chip-select IDs.
49 nand-ecc-mode:
51 Desired ECC engine, either hardware (most of the time
52 embedded in the NAND controller) or software correction
54 and should be replaced by soft and nand-ecc-algo.
56 enum: [none, soft, hw, hw_syndrome, hw_oob_first, on-die]
58 nand-ecc-engine:
60 - $ref: /schemas/types.yaml#/definitions/phandle
62 A phandle on the hardware ECC engine if any. There are
64 1/ The ECC engine is part of the NAND controller, in this
66 2/ The ECC engine is part of the NAND part (on-die), in this
68 3/ The ECC engine is external, in this case the phandle should
69 reference the specific ECC engine node.
71 nand-use-soft-ecc-engine:
73 description: Use a software ECC engine.
75 nand-no-ecc-engine:
77 description: Do not use any ECC correction.
79 nand-ecc-placement:
81 - $ref: /schemas/types.yaml#/definitions/string
82 - enum: [ oob, interleaved ]
84 Location of the ECC bytes. This location is unknown by default
85 but can be explicitly set to "oob", if all ECC bytes are
86 known to be stored in the OOB area, or "interleaved" if ECC
89 nand-ecc-algo:
91 Desired ECC algorithm.
95 nand-bus-width:
97 Bus width to the NAND chip
102 nand-on-flash-bbt:
108 it as the device ages. Otherwise, the out-of-band area of a
113 nand-ecc-strength:
115 Maximum number of bits that can be corrected per ECC step.
119 nand-ecc-step-size:
121 Number of data bytes covered by a single ECC step.
125 nand-ecc-maximize:
128 Whether or not the ECC strength should be maximized. The
129 maximum ECC strength is both controller and chip
130 dependent. The ECC engine has to select the ECC config
133 only the in-band area is used by the upper layers, and you
134 want to make your NAND as reliable as possible.
136 nand-is-boot-medium:
139 Whether or not the NAND chip is a boot medium. Drivers might
140 use this information to select ECC algorithms supported by
143 nand-rb:
144 $ref: /schemas/types.yaml#/definitions/uint32-array
148 rb-gpios:
152 Ready/Busy pins. Active state refers to the NAND ready state and
156 - reg
159 - "#address-cells"
160 - "#size-cells"
165 - |
166 nand-controller {
167 #address-cells = <1>;
168 #size-cells = <0>;
172 nand@0 {
174 nand-ecc-mode = "soft";
175 nand-ecc-algo = "bch";
177 /* NAND chip specific properties */