Lines Matching full:port

34 - reg: Port address described must be 6 for CPU port and from 0 to 5 for
36 - phy-mode: String, the following values are acceptable for port labeled
43 Port 5 of mt7530 and mt7621 switch is muxed between:
45 2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC
46    of the SOC. Used in many setups where port 0/4 becomes the WAN port.
51 Port 5 modes/configurations:
52 1. Port 5 is disabled and isolated: An external phy can interface to the 2nd
54    In the case of a build-in MT7530 switch, port 5 shares the RGMII bus with 2nd
56 2. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC.
57    It is a simple MAC to PHY interface, port 5 needs to be setup for xMII mode
59 3. Port 5 is muxed to GMAC5 and can interface to an external phy.
60    Port 5 becomes an extra switch port.
63 4. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as 2nd CPU port.
64    Currently a 2nd CPU port is not supported by DSA code.
69    a ethernet port. But can't interface to the 2nd GMAC.
71 Based on the DT the port 5 mode is configured.
74 When phy-handle matches PHY of port 0 or 4 then port 5 set-up as mode 2.
100 				port@0 {
105 				port@1 {
110 				port@2 {
115 				port@3 {
120 				port@4 {
125 				port@6 {
139 Example 2: MT7621: Port 4 is WAN port: 2nd GMAC -> Port 5 -> PHY port 4.
185 				port@0 {
190 				port@1 {
195 				port@2 {
200 				port@3 {
205 /* Commented out. Port 4 is handled by 2nd GMAC.
206 				port@4 {
212 				cpu_port0: port@6 {
229 Example 3: MT7621: Port 5 is connected to external PHY: Port 5 -> external PHY.
268 				port@0 {
273 				port@1 {
278 				port@2 {
283 				port@3 {
288 				port@4 {
293 				port@5 {
300 				cpu_port0: port@6 {