Lines Matching full:port

20 mdio-bus each subnode describing a port needs to have a valid phandle
22 N:N mapping of port and PHY id.
27 The CPU port of this switch is always port 0.
29 A CPU port node has the following optional node:
79 				port@0 {
90 				port@1 {
96 				port@2 {
102 				port@3 {
108 				port@4 {
114 				port@5 {
138 				port@0 {
149 				port@1 {
154 				port@2 {
159 				port@3 {
164 				port@4 {
169 				port@5 {