Lines Matching +full:ethernet +full:- +full:switch
1 Properties for an MDIO bus multiplexer/switch controlled by GPIO pins.
8 - compatible : mdio-mux-gpio.
9 - gpios : GPIO specifiers for each GPIO line. One or more must be specified.
16 compatible = "cavium,octeon-3860-mdio";
17 #address-cells = <1>;
18 #size-cells = <0>;
23 An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
27 mdio-mux {
28 compatible = "mdio-mux-gpio";
30 mdio-parent-bus = <&smi1>;
31 #address-cells = <1>;
32 #size-cells = <0>;
36 #address-cells = <1>;
37 #size-cells = <0>;
39 phy11: ethernet-phy@1 {
41 marvell,reg-init = <3 0x10 0 0x5777>,
45 interrupt-parent = <&gpio>;
48 phy12: ethernet-phy@2 {
50 marvell,reg-init = <3 0x10 0 0x5777>,
54 interrupt-parent = <&gpio>;
57 phy13: ethernet-phy@3 {
59 marvell,reg-init = <3 0x10 0 0x5777>,
63 interrupt-parent = <&gpio>;
66 phy14: ethernet-phy@4 {
68 marvell,reg-init = <3 0x10 0 0x5777>,
72 interrupt-parent = <&gpio>;
79 #address-cells = <1>;
80 #size-cells = <0>;
82 phy21: ethernet-phy@1 {
84 marvell,reg-init = <3 0x10 0 0x5777>,
88 interrupt-parent = <&gpio>;
91 phy22: ethernet-phy@2 {
93 marvell,reg-init = <3 0x10 0 0x5777>,
97 interrupt-parent = <&gpio>;
100 phy23: ethernet-phy@3 {
102 marvell,reg-init = <3 0x10 0 0x5777>,
106 interrupt-parent = <&gpio>;
109 phy24: ethernet-phy@4 {
111 marvell,reg-init = <3 0x10 0 0x5777>,
115 interrupt-parent = <&gpio>;