Lines Matching +full:axi +full:- +full:config
1 * Mobiveil AXI PCIe Root Port Bridge DT description
7 - #address-cells: Address representation for root ports, set to <3>
8 - #size-cells: Size representation for root ports, set to <2>
9 - #interrupt-cells: specifies the number of cells needed to encode an
11 - compatible: Should contain "mbvl,gpex40-pcie"
12 - reg: Should contain PCIe registers location and length
15 "csr_axi_slave" : Bridge config registers
20 - device_type: must be "pci"
21 - apio-wins : number of requested apio outbound windows
22 default 2 outbound windows are configured -
23 1. Config window
25 - ppio-wins : number of requested ppio inbound windows
27 - bus-range: PCI bus numbers covered
28 - interrupt-controller: identifies the node as an interrupt controller
29 - #interrupt-cells: specifies the number of cells needed to encode an
31 - interrupts: The interrupt line of the PCIe controller
34 - interrupt-map-mask,
35 interrupt-map: standard PCI properties to define the mapping of the
37 - ranges: ranges for the PCI memory regions (I/O space region is not
46 #address-cells = <3>;
47 #size-cells = <2>;
48 compatible = "mbvl,gpex40-pcie";
53 reg-names = "config_axi_slave",
58 apio-wins = <2>;
59 ppio-wins = <1>;
60 bus-range = <0x00000000 0x000000ff>;
61 interrupt-controller;
62 interrupt-parent = <&gic>;
63 #interrupt-cells = <1>;
65 interrupt-map-mask = <0 0 0 7>;
66 interrupt-map = <0 0 0 0 &pci_express 0>,