Lines Matching +full:0 +full:x3000
23 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
32 registers area. This range entry translates the '0x82000000 0 r' PCI
33 address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
34 of the internal register window (as identified by MBUS_ID(0xf0,
35 0x01)).
39 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
79 value is 0.
93 bus-range = <0x00 0xff>;
97 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
98 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
99 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
100 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
101 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
102 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
103 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
104 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
105 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
106 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
107 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
108 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
109 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
110 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
111 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
112 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
113 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
114 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
116 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
117 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
118 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
119 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
120 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
121 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
122 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
123 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
125 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
126 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
128 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
129 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
131 pcie@1,0 {
133 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
134 reg = <0x0800 0 0 0 0>;
138 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
139 0x81000000 0 0 0x81000000 0x1 0 1 0>;
140 interrupt-map-mask = <0 0 0 0>;
141 interrupt-map = <0 0 0 0 &mpic 58>;
142 marvell,pcie-port = <0>;
143 marvell,pcie-lane = <0>;
151 pcie@2,0 {
153 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
154 reg = <0x1000 0 0 0 0>;
158 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
159 0x81000000 0 0 0x81000000 0x2 0 1 0>;
160 interrupt-map-mask = <0 0 0 0>;
161 interrupt-map = <0 0 0 0 &mpic 59>;
162 marvell,pcie-port = <0>;
167 pcie@3,0 {
169 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
170 reg = <0x1800 0 0 0 0>;
174 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
175 0x81000000 0 0 0x81000000 0x3 0 1 0>;
176 interrupt-map-mask = <0 0 0 0>;
177 interrupt-map = <0 0 0 0 &mpic 60>;
178 marvell,pcie-port = <0>;
183 pcie@4,0 {
185 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
186 reg = <0x2000 0 0 0 0>;
190 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
191 0x81000000 0 0 0x81000000 0x4 0 1 0>;
192 interrupt-map-mask = <0 0 0 0>;
193 interrupt-map = <0 0 0 0 &mpic 61>;
194 marvell,pcie-port = <0>;
199 pcie@5,0 {
201 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
202 reg = <0x2800 0 0 0 0>;
206 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
207 0x81000000 0 0 0x81000000 0x5 0 1 0>;
208 interrupt-map-mask = <0 0 0 0>;
209 interrupt-map = <0 0 0 0 &mpic 62>;
211 marvell,pcie-lane = <0>;
215 pcie@6,0 {
217 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
218 reg = <0x3000 0 0 0 0>;
222 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
223 0x81000000 0 0 0x81000000 0x6 0 1 0>;
224 interrupt-map-mask = <0 0 0 0>;
225 interrupt-map = <0 0 0 0 &mpic 63>;
231 pcie@7,0 {
233 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
234 reg = <0x3800 0 0 0 0>;
238 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
239 0x81000000 0 0 0x81000000 0x7 0 1 0>;
240 interrupt-map-mask = <0 0 0 0>;
241 interrupt-map = <0 0 0 0 &mpic 64>;
247 pcie@8,0 {
249 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
250 reg = <0x4000 0 0 0 0>;
254 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
255 0x81000000 0 0 0x81000000 0x8 0 1 0>;
256 interrupt-map-mask = <0 0 0 0>;
257 interrupt-map = <0 0 0 0 &mpic 65>;
263 pcie@9,0 {
265 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
266 reg = <0x4800 0 0 0 0>;
270 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
271 0x81000000 0 0 0x81000000 0x9 0 1 0>;
272 interrupt-map-mask = <0 0 0 0>;
273 interrupt-map = <0 0 0 0 &mpic 99>;
275 marvell,pcie-lane = <0>;
279 pcie@a,0 {
281 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
282 reg = <0x5000 0 0 0 0>;
286 ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
287 0x81000000 0 0 0x81000000 0xa 0 1 0>;
288 interrupt-map-mask = <0 0 0 0>;
289 interrupt-map = <0 0 0 0 &mpic 103>;
291 marvell,pcie-lane = <0>;