Lines Matching full:pcie

1 * Marvell EBU PCIe interfaces
6     marvell,armada-370-pcie
7     marvell,armada-xp-pcie
8     marvell,dove-pcie
9     marvell,kirkwood-pcie
15 - ranges: ranges describing the MMIO registers to control the PCIe
17   the memory and I/O regions of each PCIe interface.
28   registers of this PCIe interface, from the base of the internal
46    * s is the PCI slot that corresponds to this PCIe interface
58 PCIe interface, having the following mandatory properties:
63   this PCIe interface.
64 - clocks: the clock associated to this PCIe interface
65 - marvell,pcie-port: the physical PCIe port number
74   define the mapping of the PCIe interface to interrupt numbers.
77 - marvell,pcie-lane: the physical PCIe lane number, for ports having
82   specified will default to 100ms, as required by the PCIe specification.
86 pcie-controller {
87 	compatible = "marvell,armada-xp-pcie";
131 	pcie@1,0 {
142 		marvell,pcie-port = <0>;
143 		marvell,pcie-lane = <0>;
151 	pcie@2,0 {
162 		marvell,pcie-port = <0>;
163 		marvell,pcie-lane = <1>;
167 	pcie@3,0 {
178 		marvell,pcie-port = <0>;
179 		marvell,pcie-lane = <2>;
183 	pcie@4,0 {
194 		marvell,pcie-port = <0>;
195 		marvell,pcie-lane = <3>;
199 	pcie@5,0 {
210 		marvell,pcie-port = <1>;
211 		marvell,pcie-lane = <0>;
215 	pcie@6,0 {
226 		marvell,pcie-port = <1>;
227 		marvell,pcie-lane = <1>;
231 	pcie@7,0 {
242 		marvell,pcie-port = <1>;
243 		marvell,pcie-lane = <2>;
247 	pcie@8,0 {
258 		marvell,pcie-port = <1>;
259 		marvell,pcie-lane = <3>;
263 	pcie@9,0 {
274 		marvell,pcie-port = <2>;
275 		marvell,pcie-lane = <0>;
279 	pcie@a,0 {
290 		marvell,pcie-port = <3>;
291 		marvell,pcie-lane = <0>;